Display device wherein drive currents are based on gradation currents and method for driving a display device

ABSTRACT

A display device that displays image information in response to a digital display signal includes a display panel signal lines and scanning lines which intersect at right angles with each other, and a plurality of display pixels with optical elements arranged near the intersecting points of the signal lines and scanning lines. A signal driver circuit has a plurality of current generation circuits including a drive current generation circuit for generating drive current from a plurality of gradation currents based on the display signal value supplied to each of the scanning lines, a scanning driver circuit for sequentially applying a scanning signal to each of the scanning lines for setting the selection state of each line of each display pixel, and a gradation current generation circuit for generating gradation currents according to each display signal bit at least based on a constant predetermined reference current.

This application is a U.S. National Phase Application under 35 USC 371of International Application PCT/JP2003/013819 filed Oct. 29, 2003.

BACKGROUND OF THE INVENTION

This invention relates to a display device which displays desired imageinformation on a display panel comprising a plurality of display pixelswhich have current drive type optical elements, and more particularlyregarding a display device and the method for driving the displaydevice.

In recent years, personal computer and visual equipment monitors with anelectronic screen called a Cathode Ray Tube (CRT) are fast becomingobsolete with the emergence of flat panel display devices, such asLiquid Crystal Display (LCD) flat panel monitors, at an astonishingrate. In particular, LCD's are commonplace because they offer some realadvantages over other display technologies. They are thinner, lighterand draw much less power than conventional CRT's. LCD's are all aroundus everyday as they come in all shapes and sizes ranging from largescreen televisions to small laptop computers and Personal DigitalAssistants (PDA's), and even smaller cellular phones, digital camerasand many other electronic devices.

As the display device (display) of the next generation following in thisrevolutionary LCD technology, such as organic electroluminescent (EL)devices (hereinafter referred to as organic EL devices), inorganicelectroluminescent elements (hereinafter referred to as inorganic ELelements), or Light Emitting Diodes (LEDs) and the like, full-scaleapplication of the self-light type display (display device) comprising adisplay panel configured with self-light type light emitting elementscalled active matrix is evolving. Specifically, an active matrix is atype of LCD where each display element (each pixel) includes an activecomponent such as a transistor to maintain its state between scans, andis also known as Thin-Film Transistor or TFT.

In such a self-light generation display, notably, a self-light typedisplay which applies an active matrix drive method as compared withLCD's, the display speed response is fast with an unrestricted viewingangle. Also, higher luminosity, higher contrast, high definition displaypanels with much lower power consumption and the like are inevitable inthe future. Since backlight is not needed in such an LCD display, it hasvery predominant characteristics that still more thinly shaped andlightweight models are possible.

This particular type of display panel, briefly, is comprises an array ofdisplay pixels which contain light emitting elements arranged near eachof the intersecting points of the signal lines and in the direction ofthe scanning lines set in the line writing direction; a scanning driverapplies sequentially scanning signals to predetermined timing and setsthe display pixels of a specified line in a selection state; and a datadriver generates write-in current (drive current) according to thedisplay data which is supplied to each of the display pixels via signallines and the above-mentioned write-in current is supplied to each ofthe display pixels. Each of the light emitting elements performs a lightgeneration operation by predetermined luminosity gradation according tothe display data, and the desired image information is displayed on thedisplay panel. Afterwards, the configuration of a self-light generationtype display will be described.

In the display drive operation of such a display, individual write-incurrents are generated which have a current value according to thedisplay data from the data driver to a plurality of display pixels andsupplied simultaneously to the display pixels of a specified lineselected by the scanning driver. This is in contrast to a currentspecification type drive method which repeats successively an operationto make each light emitting element emit light by predeterminedluminosity gradation for each line of one screen and the display pixelsof a specified line selected by a scanning driver. A Pulse WidthModulation (PWM) type drive method and the like which repeatssuccessively for one screen an operation which supplies constant drivecurrent of a constant value from the data driver, individual time width(signal width) according to the display data, and makes each of thelight emitting elements emit light by predetermined luminosity gradationis commonly known.

However, there is a problem in the light emitting element type displaymentioned above and the fact they do suffer from this drawback will beexplained below.

Specifically, the data driver generates the write-in current accordingto the display data corresponding to each of the display pixels and theabove-mentioned write-in current changes according to the display datain a conventional configuration and a conventional drive controllingmethod, which are supplied to the display pixels via each of the signallines connected to an output terminal of the data driver. Thus, thecurrent supplied to a circuit arrangement of transistors, latch circuitsand the like which are individually formed in the data drivercorresponding to each of the signal lines from a predetermined currentsource will also change. Here, generally a capacitative element (wiringcapacity) exists in the signal wiring. Consequently, current suppliedfrom the above-mentioned current source to the data driver, whensupplied to the circuit arrangement via the signal wiring for currentsupply, the operation which alters the current supplied from the currentsource is equivalent to the charge or discharging of predeterminedelectric potential in parasitic capacitance which exists in the signalwiring. As a result, when the current supplied via the signal wiring isextremely low, the charge and discharge operation of the signal wiringfor current supply takes time, and by the time the electric potential ofthe signal lines are stabilized, a relatively lengthy period will berequired.

On the other hand, the operational period assigned to a current holdingoperation and the like in each of the signal lines becomes brief andattains high-speed operation essential in the data driver so the numberof signal lines increases in proportion to the buildup of the number ofdisplay pixels of the display panel.

However, as mentioned above, the charge and discharge operation of thecurrent supply in the signal wiring requires a certain amount of time,particularly; the current value of the write-in current supplied via thesignal lines to the display panel in connection with miniaturization ofthe display panel or high definition (high resolution) and the likebecomes low. It has disadvantages in the amount of time required in thecharge and discharge operation of the signal wiring increases, ratecontrolling of the operating speed of data driver due to the rate of thecharge and discharge operation has to be performed and achievingfavorable image quality becomes difficult.

Additionally, display devices comprising a conventional data driver areconfigured so the write-in current is generated according to the displaydata by the data driver and supplied to the display pixels via eachsignal line. However, because the write-in current is an analog signalwhich changes according to the light generation state of the lightemitting elements, the signal is easily influenced by external noise orsignal degradation which produces a decline or change in the lightgeneration luminosity in the light emitting elements. This problem makesit difficult to obtain a stable image display in suitable luminositygradation.

SUMMARY OF THE INVENTION

The present invention has been made in view of the circumstancesmentioned above. Accordingly, the present invention has an advantage toprovide a display device which displays image information in response toa display signal on a display panel which has display pixels that havecurrent drive type optical elements to enhance the operating speed withregard to generation of drive current in response to the display signalssupplied to the optical elements, even in the case of reduced drivecurrent during periods of low gradation; to reduce the amount of timerequired for generation of the drive current; and to improve the displayresponse characteristics with the resultant effect to achieve favorabledisplay image quality.

To achieve the foregoing advantage, the first display device in thepresent invention comprises a display panel with a plurality of signallines and a plurality of scanning lines which intersect at right angleswith each other, and a plurality of display pixels with optical elementsarranged near the intersecting point of the plurality of signal linesand the plurality of scanning lines; a scanning driver circuit forsequentially applying a scanning signal to each of the scanning linesfor setting the selective state of each line of each display pixel; anda signal driver circuit comprises a plurality of current generationcircuits; the current generation circuits comprise at least a gradationcurrent generation circuit and a drive current generation circuit; thegradation current generation circuit generates a plurality of gradationcurrents corresponding to each of the display signal bits based onconstant, predetermined reference current, and the drive currentgeneration circuit generates drive current from a plurality of gradationcurrents based on the value of the display signals which supplies thegenerated drive current to each signal line.

According to the display device of this invention, each of the currentgeneration circuits in the above-mentioned signal drive circuit furthercomprise a signal holding circuit which takes in and holds the displaysignal; selects and integrates the gradation currents according each bitvalue of the display signal from the plurality of gradation currentsbased on a value of the signals held in the signal holding circuit andgenerates drive current.

According to the present invention, each of the current generationcircuits generate a plurality of gradation currents which comprises aplurality of gradation current transistors, wherein the channel width ofeach the gradation current transistors is set at a different ratio witheach other specified by 2n. Each control terminal thereof is connectedin parallel and the gradation currents flow in the current path of eachof the gradation current transistors. Furthermore, each of the gradationcurrent generation circuits comprise a reference voltage generationcircuit for generating reference voltage based on the reference current.The reference voltage generation circuits comprise reference currenttransistors for generating reference voltage to the control terminals,and the reference current is supplied to the current path. The referencecurrent transistor control terminals are connected in common to thecontrol terminals of a plurality of gradation current transistors. Thereference current transistors and the plurality of gradation currenttransistors constitute a current mirror circuit.

In addition, according to the present invention, the signal drivercircuit comprises a configuration in which the reference current issupplied to a plurality of gradation current generation circuits. Thereference current is supplied via a reference current supply line. Eachof the gradation generation circuit comprises a supply control switchingcircuit for controlling the supply state of the reference current fromthe reference current supply line to the proper gradation currentgeneration circuit. The supply control switching circuit synchronizes totiming when taking in and holding the display signals for the signalholding means in each of the current generation circuits, andselectively performs switching control so that the reference current issupplied only to any one of the gradation current circuits of theplurality of gradation current generation circuits.

According to the present invention, each of the current generationcircuits comprise a specified state setting circuit for setting thesignal line to a specified voltage which makes the optical elementsdrive in a specified operating state when the display signal has aspecified value. The display signal specified value is a value fromwhich all of each of the gradation currents is non-selected from thedisplay signals. The specified voltage is the voltage for setting theoptical elements drive in a state of lowest gradation.

In addition, according to the present invention, each of the currentgeneration circuits further comprises a reset circuit for applyingpredetermined reset voltage to the signal lines in advance of the timingwhich supplies the drive current to the signal lines. The reset voltageis at least the low potential voltage for discharging the electriccharge stored up in the capacitative element attached to the opticalelements in the display pixels and for initializing the opticalelements. The reset voltage is applied when the display signal specifiedvalue presupposes non-selection of all of the plurality of gradationcurrents.

Moreover, according to the present invention, the optical elements inthe display pixels comprise light emitting elements for accomplishinglight generation operation by way of luminosity gradation according tothe current value of the supply current. For example, the opticalelements have light emitting elements consisting of organic EL devices.The display pixels comprise at least a pixel driver circuit which has avoltage holding circuit for holding the voltage component in response tothe drive current supplied by the signal driver circuit; and a currentsupply circuit for supplying luminescent drive current to the lightemitting elements based on the voltage component held in the voltageholding circuit and for making the light emitting elements emit light.The current supply circuit comprises transistors for use of luminescentdrive for supplying luminescent current to the light emitting elements.

To achieve the foregoing advantage, the second display device in thepresent invention set to a display device for displaying imageinformation according to display signals consisting of digital signalscomprises: (1) a display panel equipped with a plurality of displaypixels equipped with a current generation circuit; the currentgeneration circuit comprises a plurality of signal lines and a pluralityof scanning lines which intersect at right angles with each other; atleast optical elements formed of the current drive type and arrangedclose to the intersecting point of a plurality of signal lines and aplurality of scanning lines; a gradation current generation circuit forgenerating a plurality of gradation currents corresponding to each ofthe display signal bits based on predetermined, constant referencecurrent; a drive current generation circuit for generating drive currentbased on the value of the display signals which supplies the drivecurrent to the optical elements; (2) a scanning driver circuit forsequentially applying a scanning signal for setting the selective stateof each line of each scanning line; and (3) a signal driver circuit forsupplying the display signals to a plurality of signal lines.

According to the present invention, the current generation circuitcomprises a signal holding circuit which takes in the display signalsand holds the signals based on the value of the display signals held inthe holding circuit; selects and integrates the gradation currentsaccording each bit value of the display signal from the plurality ofgradation currents; and generates drive current.

According to the present invention, according to the present invention,each of gradation current generation circuits generate a plurality ofgradation currents which comprise a plurality of gradation currenttransistors, wherein the channel width of each of the gradation currenttransistors are set at a different ratio with each other specified by2n. Each control terminal thereof is connected in parallel and thegradation currents flow in the current path of each of the gradationcurrent transistors. Also, each of the gradation current generationcircuits comprise a reference voltage generation circuit for generatingreference voltage based on the reference current. The reference voltagegeneration circuits comprise reference current transistors forgenerating reference voltage to the control terminals, and the referencecurrent is supplied to the current path. The reference currenttransistor control terminals are connected in common to the controlterminals of a plurality of gradation current transistors. The referencecurrent transistors and the plurality of gradation current transistorsconstitute a current mirror circuit.

According to the present invention, each of the current generationcircuits comprise a specified state setting circuit for setting thesignal line to a specified voltage which makes the optical elementsdrive in a specified operating state when the display signal has aspecified value. The display signal specified value is a value fromwhich all of each of the gradation currents is non-selected from thedisplay signals. The specified voltage is the voltage for setting theoptical elements drive in a state of lowest gradation.

In addition, according to the present invention, each of the currentgeneration circuits further comprises a reset circuit for applyingpredetermined reset voltage to the signal lines in advance of thetiming, which supplies the drive current to the signal lines. The resetvoltage is at least the low potential voltage for discharging theelectric charge stored up in the capacitative element added in theoptical elements in the display pixels and for initializing the opticalelements. The reset voltage is applied when the display signal specifiedvalue presupposes non-selection of all of the plurality of gradationcurrents.

According to the present invention, the optical elements in the displaypixels comprise light emitting elements for accomplishing lightgeneration operation by way of luminosity gradation according to thecurrent value of the supply current. For example, the optical elementshave light emitting elements consisting of organic EL devices.

Additionally, according to the present invention, the reference currenttransistors, the gradation current transistors and the light generationdrive at least any has a configuration of transistors comprising a bodyterminal electrode.

The above and further objects and novel features of the presentinvention will more fully appear from the following detailed descriptionwhen the same is read in conjunction with the accompanying drawings. Itis to be expressly understood, however, that the drawings are for thepurpose of illustration only and are not intended as a definition of thelimits of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an outline block diagram showing the first embodiment of thecurrent generation circuit in the display device related to thisinvention.

FIG. 2 is a circuit arrangement drawing showing one example of the latchcircuits applied to the current generation circuit in this embodiment.

FIG. 3 is a circuit arrangement drawing showing one example of thecurrent generation section applied to the current generation circuit inthis embodiment.

FIG. 4 is an outline block diagram showing the second embodiment of thecurrent generation circuit in the display device related to thisinvention.

FIG. 5 is a circuit arrangement drawing showing one example of thecurrent generation section applied to the current generation circuit inthis embodiment.

FIG. 6 is an outline block diagram showing the third embodiment of thecurrent generation circuit in the display device related to thisinvention.

FIG. 7 is a circuit arrangement drawing showing an example of thedetailed configuration of the logic circuit applicable to the specifiedstate setting section of the current generation circuit in thisembodiment.

FIG. 8 is an outline block diagram showing the fourth embodiment of thecurrent generation circuit in the display device related to thisinvention.

FIGS. 9A and 9B are circuit arrangement drawings showing examples of thedetailed configuration of the logic circuit applicable to the specifiedstate setting section of the current generation circuit in thisembodiment.

FIG. 10 is an outline block diagram showing one example of the currentgeneration section applied to the fifth embodiment of the currentgeneration circuit in the display device related to this invention.

FIG. 11 is a drawing showing an example of the detailed circuit of thecurrent generation section of the current generation circuit in thisembodiment.

FIG. 12 is an outline block diagram showing another example of thecurrent generation section applied to the current generation circuit inthis embodiment.

FIG. 13 is an outline block diagram showing the first embodiment of thedisplay device related to this invention.

FIG. 14 is an outline block diagram showing an example of theconfiguration of the display panel applied to the display device relatedto this embodiment.

FIG. 15 is an outline block diagram showing another example of theconfiguration of the display device related to this embodiment.

FIG. 16 is a circuit arrangement drawing showing an example of oneconfiguration of the pixel driver circuit corresponding to the currentsinking method applicable to the display device related to thisembodiment.

FIG. 17 is a circuit arrangement drawing showing the configuration ofthe first embodiment of the data driver in the display device concerningthis invention.

FIG. 18 is a timing chart which shows an example of the drive controloperation of the data driver in this embodiment.

FIG. 19 is a timing chart which shows an example of the drive controloperation of the display panel in this embodiment.

FIG. 20 is a circuit arrangement drawing showing the configuration ofthe second embodiment of the data driver in the display device relatedto this invention.

FIG. 21 is a circuit arrangement drawing showing an example of oneconfiguration of the pixel driver circuit corresponding to the currentapplication method applicable to the display device in this embodiment.

FIG. 22 is an outline block diagram showing an example of a currentgeneration circuit applied to the third embodiment of the data driver inthe display device concerning this invention.

FIG. 23 is an outline block diagram showing another example of thecurrent generation circuit applied to the data driver in thisembodiment.

FIG. 24 is a circuit arrangement drawing showing the configuration ofthe fourth embodiment of the data driver in the display device relatedto this invention.

FIG. 25 is a circuit arrangement drawing showing one example of thewrite-in current generation circuit applied to the data driver in thisembodiment.

FIGS. 26A and 26B are circuit arrangement drawings showing examples ofthe inverted latch circuit applied to the data driver in this embodimentand the selection setting circuit.

FIG. 27 is a timing chart which shows an example of the drive controloperation in the data driver of this embodiment.

FIG. 28 is a circuit arrangement drawing showing the configuration ofthe fifth embodiment of the data driver in the display device related tothis invention.

FIG. 29 is a circuit arrangement drawing showing one example of thewrite-in current generation circuit applied to the data driver in thisembodiment.

FIG. 30 is a circuit arrangement drawing showing the configuration ofthe sixth embodiment of the data driver in the display device related tothis invention.

FIG. 31 is a circuit arrangement drawing applicable to the displaydevice in this embodiment showing another example of the configurationof the pixel driver circuit corresponding to the current applicationmethod.

FIG. 32 is a timing chart which shows an example of the drive controloperation in the data driver of this embodiment.

FIG. 33 is a timing chart which shows an example of the drive controloperation of the display panel in this embodiment.

FIG. 34 is a circuit arrangement drawing showing a configuration of theseventh embodiment of the data driver in the display device related tothis invention.

FIG. 35 is a circuit arrangement drawing applicable to the displaydevice in this embodiment showing another example of the configurationof the pixel driver circuit corresponding to the current sinking method.

FIG. 36 is a circuit arrangement drawing showing the configuration ofthe eighth embodiment of the data driver in the display device relatedto this invention.

FIG. 37 is a timing chart which shows an example of the drive controloperation of the data driver in this embodiment.

FIG. 38 is a circuit arrangement drawing showing another example of theconfiguration which is the display pixels applicable to the displaydevice concerning this invention.

FIG. 39 is a circuit arrangement drawing showing another example of theconfiguration of the display pixels applicable to the display devicerelated to this invention.

FIG. 40 is a timing chart which shows an example of the drive controloperation in the display device related to this embodiment.

FIG. 41 is an outline block diagram showing an example of oneconfiguration of the second embodiment of the display device related tothis invention.

FIG. 42 is a circuit arrangement drawing showing one embodiment of thepixel driver circuit applied to the display device in this embodiment.

FIG. 43 is a circuit arrangement drawing showing one embodiment of thedata driver applied to the display device in this embodiment.

FIG. 44 is a timing chart which shows an example of the drive controloperation in the display device in this embodiment.

FIG. 45 is a circuit arrangement drawing showing another embodiment ofthe pixel driver circuit applied to the display device in thisembodiment.

FIG. 46 is an outline block diagram showing another example of theconfiguration in the display device of this embodiment.

FIG. 47 is a circuit arrangement drawing showing another embodiment ofthe pixel driver circuit applied to the display device in thisembodiment.

FIGS. 48A-48B are drawings showing the basic circuit and voltage-currentcharacteristics of an Nch Thin-Film Field-Effect Transistor in aconventional configuration.

FIGS. 49A-49B are drawings showing the basic circuit and voltage-currentcharacteristics of a Pch Thin-Film Field-Effect Transistor in aconventional configuration.

FIGS. 50A-50B are drawings showing the connection between thevoltage-current characteristics in the transistor for the lightgeneration drive (Pch transistor), and the current value of the draincurrent (light generation drive current) which is set at the time of thewrite-in operation and the light generation operation.

FIGS. 51A-51B are schematic diagrams showing a level surfaceconfiguration of a Pch Thin-Film Transistor which has a body terminalconfiguration.

FIGS. 52A-52D are schematic diagrams showing a cross-sectionalconfiguration of a Pch Thin-Film Transistor which has a body terminalconfiguration.

FIGS. 53A-53B are drawings showing the basic circuit of an Nch Thin-FilmTransistor which has a body terminal configuration and thevoltage-current characteristics.

FIGS. 54A-54B are drawings showing the basic circuit of a Pch Thin-FilmTransistor which has a body terminal configuration and thevoltage-current characteristics.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will hereinafter be described in detail withreference to the preferred embodiments shown in the accompanyingdrawings is applied to a display device and a drive method of thedisplay device related to this invention.

First, the configuration of the data driver in the display devicerelated to this invention or a current generation circuit is applied toa pixel driver circuit, and a controlling method of the currentgeneration circuit will be explained with reference to the drawings.

1. Current Generation Circuit

<<The First Embodiment of a Current Generation Circuit>>

Initially, the first embodiment of the current generation circuit in thedisplay device related to this invention will be explained withreference to the drawings.

FIG. 1 is an outline block diagram showing the first embodiment of thecurrent generation circuit in the display device related to thisinvention.

As shown in FIG. 1, the current generation circuit ILA related to thisembodiment has a configuration formed with a signal latch section 10(signal holding circuit) and a current generation section 20A. Thesignal latch section 10 comprises latch circuits LC0, LC1, LC2 and LC3(LC0-LC3) which take in individually a plurality of bits (A case of fourbits is illustrated in this embodiment) of the digital signals d0, d1,d2 and d3 (d0-d3) for specifying a current value and hold them (latch orlatches, as applicable). A current generation section 20A outputs to aload current supply line CL connected to a load which takes in areference current Iref that has a constant current value supplied from acurrent generator IRA, and generates a drive current ID that has acurrent value of a predetermined ratio as opposed to the referencecurrent Iref based on the output signals d10, d11, d12 and d13 (d10-d13)output from the above-mentioned signal latch section 10 (each of thelatch circuits (LC0-LC3).

Here, the current generator IRA is connected to a voltage contact +Vconnected to high supply voltage to flow reference current Iref in thedirection of the current generation section 20A through a referencecurrent supply line Ls.

Hereafter, the above-mentioned configuration will be explained indetail.

FIG. 2 is a circuit arrangement drawing showing one example of the latchcircuits applied to the current generation circuit in this embodiment.

FIG. 3 is a circuit arrangement drawing showing one example of thecurrent generation section applied to the current generation circuit inthis embodiment.

The signal latch section 10, as shown in FIG. 1, a number of the latchcircuits LC0-LC3 are formed in parallel according to the number ofdigital signals d0-d3 bits (4 bits); takes in simultaneously theabove-mentioned digital signals d0-d3 supplies each one individuallybased on a timing control signal CLK output from a timing generator, ashift register and the like (omitted from the diagram); and performs anoperation which holds and outputs signal levels based on the properdigital signals d0-d3.

Here, each of the latch circuits LC0-LC3 which constitute the signallatch section 10, as shown in FIG. 2, have a configuration comprising aplurality of universally known Complementary Metal Oxide Semiconductor(CMOS) type transistor circuits, which are connected in series top-channel type (hereinafter referred to as Pch transistor) and n-channeltype (hereinafter referred to as Nch transistor) Metal OxideSemiconductor Field-Effect Transistor (MOSFET) type transistors.

Specifically, as illustrated in FIG. 2, the latch circuits LC (LC0-LC3)has a configuration comprising a CMOS 11 consisting of a Pch transistorTr1 and an Nch transistor Tr2; a CMOS 12 consisting of a Pch transistorTr3 and an Nch transistor Tr4; a CMOS 13 consisting of a Pch transistorTr5 and an Nch transistor Tr6; a CMOS 14 consisting of a Pch transistorTr7 and an Nch transistor Tr8; a CMOS 15 consisting of a Pch transistorTr9 and an Nch transistor Tr10; and a CMOS 16 consisting of a Pchtransistor Tr11 and an Nch transistor Tr12.

At the CMOS 11 input contact point (clock input terminal of latchcircuit LC) CK, the timing control signal (clock signal) CLK is suppliedand an output contact point N11 (hereinafter references to “contactpoint” will be denoted as “contact” for convenience of explanation) isconnected to the CMOS 12 input contact. Further, the above-mentionedtiming control signal CLK is supplied to the CMOS 13 input terminal. TheCMOS 13 output contact N12 connects the CMOS 12 output contact with theCMOS 14 input contact. The CMOS 14 output contact N13 is connected tothe CMOS 15 and CMOS 16 input contacts. On one side, the signal levelsof output contact N13 are output as inverse output signals from aninverted output terminal OT* (Denoted as “OT*” for convenience ofexplanation in the description and reference element in FIG. 2) of thelatch circuit LC. On the other side, the signal levels of CMOS 15 outputcontact N15 is output from a non-inverted output terminal OT of thelatch circuits LC as a non-inverted output signals.

In addition, CMOS 11, CMOS 14, CMOS 15 and CMOS 16 are constituted byeach of the Pch transistors Tr1, Tr7, Tr9 and Tr11 whereby one end ofthe current path is connected to the high supply voltage Vdd, as well aseach of the Nch transistors Tr2, Tr8, Tr10, and Tr12 whereby one end ofthe current path is connected to a low supply voltage Vgnd (voltage toground). As for the CMOS 12 Pch transistor Tr3 and the CMOS 13 Nchtransistor Tr6, one end of the current path is connected to a signalinput terminal IN of the latch circuit LC and the above-mentioneddigital signals d0-d3 are supplied. Further, CMOS 12 Nch transistor Tr4and CMOS 13 Pch transistor Tr5, one end of the current path is connectedto the above CMOS 16 output contact N14.

In the signal latch section 10 which has such a configuration, initiallywhen the timing control signal CLK (a high-level pulse signal which hasa predetermined signal width) is applied, CMOS 12 Pch transistor Tr3side and CMOS 13 Nch transistor Tr6 perform an “ON” operation, thedigital signals d0-d3 in suitable timing are taken in, and the signallevels of CMOS 12 and CMOS 13 common output contact N12 are specified bythe digital signals d0-d3. Accordingly, based on the signal levels(signal levels of the digital signals d0-d3) of the output contact N12,each signal level (high-level/low-level) of the non-inverted outputterminal OT and the inverted output terminal OT* supplied to CMOS 16output contact N14 is determined.

Here, while CMOS 12 Pch transistor Tr3 side and CMOS 13 Nch transistorTr6 performs an “OFF” operation after application of the above-mentionedtiming control signal CLK (that is, the timing control signal CLKlow-level state), the CMOS 12 Nch transistor Tr4 and CMOS 13 Pchtransistor Tr5 perform an “ON” operation. The signal level of commonoutput contact N12 of CMOS 12 AND CMOS 13 is specified, and the signallevel (equivalent to the non-inverted output signals (signal levels ofthe non-inverted output terminal OT)) of CMOS 16 output contact N14 istaken in. Accordingly, the non-inverted output signals (signal levels ofthe non-inverted output terminal OT) and the inverted output signal(signal level of inverted output terminal OT*), which have signal levelsequivalent to the time of application of the timing control signal CLK,continue and are output. The signal levels of this output signal areheld in the same output state until the signal levels (signal levels ofdigital signals d0-d3) of the signals input terminal IN changes at thetime of application of the next timing control signal CLK.

As shown in FIG. 3, a current generation section 20A comprises a currentmirror circuit (gradation current generation circuit) 21A and aswitching circuit (drive current generation circuit) 22A. The currentmirror circuit 21A generates a plurality of the gradation currents Idsa,Idsb, Idso and Idsd which have a current value of an individuallydifferent ratio (each one has a different ratio) with response toreference current Iref. The switching circuit 22A randomly selectsgradation currents from the plurality of the above-mentioned gradationcurrents Idsa-Idsd, based on the output signals d10, d11, d12, and d13(the signal levels of the non-inverted output terminal OT as illustratedin FIG. 2) from each of the latch circuits LC0-LC3 of theabove-mentioned signal latch section 10.

Specifically, as shown in FIG. 3, the current mirror circuit 21A isapplied to the current generation section 20A is configured with the Nchtransistor Tr21 (reference current transistor) and a plurality of Nchtransistors (gradation current transistors) Tr22, Tr23, Tr24,Tr25. TheNch transistor Tr21 is provided with the reference current Iref suppliedvia reference current supply line Ls connected to the current path inbetween the current input contact INi and the low supply voltage Vgnd(voltage to ground). The control terminal (gate terminal) of the Nchtransistor Tr21 (reference current transistor) is connected to thecontact Ng, along with each current path (source-drain terminals)connected in between each of the contacts Na, Nb, Nc, and Nd and the lowsupply voltage Vgnd. Each control terminal of Nch transistors (gradationcurrent transistors) Tr22, Tr23, Tr24 and Tr25 (corresponding to theplurality of latch circuits LC0-LC3) are connected in common to thecontact Ng. Here, the contact Ng is configured with a direct connectionto the current input contact INi along with a capacitor C1 connected inbetween the low supply voltage Vgnd.

The reference current transistor Tr21 generates a reference voltage Vreffor the control terminal (gate terminal: contact Ng). When the referencecurrent Iref is supplied to the current input contact INi the referencecurrent Iref flows to the current path. Each of the gradation currenttransistors Tr22-Tr25, based on the reference voltage Vref supplied toeach control terminal, gradation currents flow to each current path.

Additionally, a switching circuit 22A is applied to the currentgeneration section 20A, which has a configuration whereby the currentpath is connected between a current output contact OUTi and each of thecontacts Na, Nb, No and Nd to which a load is connected. The outputsignals d10-d13 output individually from each of the above-mentionedlatch circuits LC0-LC3 to control terminals applied in parallel with aplurality (4 devices) of Nch transistors Tr26, Tr27, Tr28 and Tr29.

Here, in the current generation section 20A as applied to thisembodiment, in particular the gradation currents Idsa-Idsd, which flowto each of the gradation current transistors Tr22-Tr25 and constitutethe current mirror circuit 21A, are set to have a current value of anindividually different predetermined ratio as opposed to the referencecurrent Iref which flows to the reference current transistor Tr21.Specifically, the transistor size of each of the gradation currenttransistors Tr22-Tr25 is an individually different ratio. For example,in the case where the fixed channel length of each of the gradationcurrent transistors Tr22-Tr25, the ratio (W2:W3:W4:W5) is formed so eachchannel width corresponds to 1:2:4:8.

Accordingly, if the channel width of the reference current transistorTr21 is presupposed as W1, the current value of the gradation currentsIdsa-Idsd which flow to each of the gradation current transistorsTr22-Tr25 will be individually set as Idsa=(W2/W1)×Iref,Idsb=(W3/W1)×Iref, Idsc=(W3/W1)×Iref, and Idsd=(W4/W1)×Iref. Thus, thecurrent value between gradation currents can be set to a ratio specifiedas 2^(n) by setting each one to the channel width of the gradationcurrent transistors Tr22-Tr25 as 2^(n) (n=0, 1, 2, 3, . . . ; 2^(n)=1,2, 4, 8, . . . ).

In this way, the current value from each of the gradation currentsIdsa-Idsd is set up to generate the drive current ID comprising thecurrent value 2^(n) step. Further described later, random gradationcurrents are selected and integrated based on the plurality of digitalsignal d0-d3 bits (output signals d10-d13). Thus, as illustrated inFIGS. 1-3, the drive current ID generated becomes 2⁴=16 differentcurrent values when the 4-bit digital signals d0-d3 are appliedaccording to the “ON” state of the transistors Tr26-Tr29 connected toeach of the gradation current transistors Tr22-Tr25.

In the current generation section 20A which has such configuration,depending upon the signal levels of the output signals d10-d13 outputfrom the above-mentioned latch circuits LC0-LC3, the particulartransistor(s) of switching circuit 22A performs an “ON” operation (Whencomprised of any one or more of the transistors Tr26-Tr29 that performan “ON” operation, other than cases of any of the transistors Tr26-Tr29that perform an “OFF” operation.). The reference current Iref flows tothe reference current transistor Tr21 to the gradation currenttransistors (any one or more of Tr22-Tr25) of the current mirror circuit22A connected to the relevant transistor(s) that performed an “ON”operation. The gradation currents Idsa-Idsd have a current value of apredetermined ratio (2^(n) gradation) and flow as mentioned above. Atthe current output contact OUTi, the drive current ID has a currentvalue consisting of a composite value of these gradation currents. Fromthe load side connected to the current output contact OUTi, the currentoutput at contact OUTi flows to the low supply voltage Vgnd via the “ON”state transistor (whichever Tr26-Tr29) and the gradation currenttransistor (whichever Tr22-Tr25).

Therefore, in the current generation circuit ILA related to thisembodiment, the drive current ID generated is converted to analogcurrent which has a predetermined current value from the currentgeneration section 20A, based on the timing specified by the timingcontrol signal CLK in response to the plurality of digital signal d0-d3bits input into signal latch section 10 and supplied to the load. (Inthis embodiment as mentioned above, the drive current is drawn in thedirection of the current generation circuit from the load side.)

Thus, in the current generation circuit ILA related to this embodiment,reference current Iref is supplied to the current generation section 20Avia the reference current supply line Ls from the current generator IRA,based on a plurality of digital signal d0-d3 bits (output signalsd10-d13 of the signal latch section 10). Specified gradation currentsare selected and integrated from a plurality of gradation currentsIdsi-Idsl which have a current value of a predetermined ratio to therelevant reference current Iref. The drive current ID is constituted sothe generated output has the desired current value. The current(reference current) supplied to the above-mentioned referenced currentsupply line Ls (signal wiring) is constant, since a current supplyvoltage fluctuation following a change is not produced. For example,even if negligible drive current is generated, there is no delay in theoperation of the current generation circuit resulting from theelectrical charge or discharge of present parasitic capacitance;thereby, the operating speed of the current generation circuit can beraised and the load can be driven at a faster speed.

Furthermore, as described later in detail, the above-mentioned pluralityof digital signal bits apply the display data on the display device forthe purpose of displaying desired image information. In this case, thedrive current generated and output by the current generation circuitcorresponds to the write-in current supplied to each display pixel whichforms the display panel or supplied to the light emitting element ofeach of the display pixels.

<<The Second Embodiment of the Current Generation Circuit>>

Next, the second embodiment of the current generation circuit related tothis invention will be explained with reference to the drawings.

FIG. 4 is an outline block diagram showing the second embodiment of thecurrent generation circuit in the display device related to thisinvention.

FIG. 5 is a circuit arrangement drawing showing one example of thecurrent generation section applied to the current generation circuit inthis embodiment.

Here, concerning any configuration equivalent in the embodimentmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

In the embodiment mentioned above, although the case illustrated isconfigured (described as “current sinking method” for convenience) fromthe load side connected to the current generation circuit ILA so thedrive current ID is drawn in the direction of current generation circuitILA, this embodiment has a configuration (described as “currentapplication method” for convenience) which flows (pours) the drivecurrent ID in the direction of the load from the current generationcircuit ILA side.

Specifically, as shown in FIG. 4, a current generation circuit ILBrelated to this embodiment has a configuration equivalent to the firstembodiment comprising the signal latch section 10 and the currentgeneration section 20B along with the current generator IRB connected tothe current generation section 20B via the reference current supply lineLs. The reference current Iref flows from the current generation section20B side in the direction of the current generator IRB connected to alow supply voltage Vgnd.

The signal latch section 10 has a configuration in which the latchcircuits LC0-LC3 are individually formed corresponding to a plurality ofthe digital signals d0-d3. The inverted output signals d10*-d13*(Denoted in the description for convenience as d10*-d13* in reference tothe same element in FIG. 4, represents the signal levels of the invertedoutput terminal OT* shown in FIG. 2.) connected to each of the latchcircuits LC0-LC3 output to the current generation section 20B.

As shown in FIG. 5, the current generation section 20B related to thisembodiment, in brief, has a current mirror circuit 21B and a switchingcircuit 22B which have a circuit arrangement resembling the firstembodiment (Reference FIG. 3) mentioned above and are almost equivalent.This section is configured so the drive current ID randomly selects andintegrates a plurality of the gradation currents Idsi, Idsj, Idsk andIdsl which have a current value of a predetermined ratio relative to thereference current Iref and generates the current supplied to the loadcurrent supply line CL, based on the output signals d10*-d13* from eachof the latch circuits LC0-LC3.

Specifically, the configuration of current mirror circuit 21B and theswitching circuit 22B consist of the Pch transistors Tr31-Tr39. Areference current transistor Tr31 is connected in between current inputcontact INi and the voltage contact +V, along with the control terminalconnected to the voltage contact +V via the current input contact INiand contact Nh together with the capacitor C1. In addition, thegradation current transistors Tr32-Tr35 are individually connected inbetween the contacts Ni, Nj, Nk and Nl and the voltage contact +V, alongwith the control terminals connected in common to the contact Nh. Also,the transistors Tr36-Tr39 for switching are configured so each one isconnected in between the above-mentioned contacts Ni, Nj, Nk and Nl andthe current output contact OUTi, along with the output signals d10*-d13*output from the latch circuits LC0-LC3 each applied to the controlterminals in parallel.

Here also set in the embodiment configuration of current mirror circuit21B, the size (Namely, the channel width at the time of setting thefixed channel length.) of each of the gradation current transistorsTr32-Tr35 is formed to correspond to a predetermined ratio based on thereference current transistor Tr31. The gradation currents Idsi-Idslwhich flow in each current path are set up so the current value of eachone is a different predetermined ratio as opposed to the referencecurrent Iref.

Therefore, also in the current generation circuit 20B related to thisembodiment, in response to the signal levels of output signals d10*-d13*output from the signal latch section 10 (the latch circuits LC0-LC3),the particular transistor(s) Tr36-Tr39 of the switching circuit 22Bperform an “ON” operation. Accordingly, the gradation currentsIdsi-Idsl, which have a current value twice the predetermined ratio ofthe reference current Iref, flows via the gradation current transistorsTr32-Tr35. These composite currents are supplied to a load connected tothe current output contact OUTi as the drive current ID via the currentoutput contact OUTi. (In this embodiment, the drive current flows in thedirection of the load from the current generation circuit side).

Also, the current generation circuit ILB of this embodiment, resemblingthe case of the first embodiment, has a configuration which selects andintegrates particular gradation currents from the plurality of gradationcurrents Idsi-Idsl to generate and output the drive current ID havingthe desired current value. Since the current (reference current)supplied to the above-mentioned reference current supply line LS (signalwiring) is constant, even if negligible drive current is generated, theoperating speed of the current generation circuit can be raised and theload can be driven at a faster speed.

<<the Third Embodiment of the Current Generation Circuit>>

Next, the third embodiment of the current generation circuit related tothis invention will be explained with reference to the drawings.

FIG. 6 is an outline block diagram showing the third embodiment of thecurrent generation circuit in the display device related to thisinvention.

FIG. 7 is a circuit arrangement drawing showing an example of thedetailed configuration of the logic circuit applicable to the specifiedstate setting section of the current generation circuit in thisembodiment.

Here, concerning any configuration equivalent in the embodimentsmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

As shown in FIG. 6, the current generation circuit ISA related to thisembodiment has a configuration equivalent to the first embodimentcomprising the signal latch section 10, the current generation section20A and a specified state setting section 30A. The specified statesetting section 30A (specified state setting circuit) has aconfiguration which applies specified voltage (Specified voltage: Ablack display voltage Vbk or a reset voltage Vr described later) to theload current supply line CL, which connects to the non-inverted outputterminal OT of the latch circuits LC0-LC3 only to drive the load by thespecified operating state.

Here, the current generator IRA connected to the voltage contact +Vconnected to the high supply voltage flows (pours) the reference currentIref in the direction of the current generation section 20A via thereference current supply line Ls.

The specified state setting section 30A, shown in FIG. 6, configurationcomprises a NOT/OR operation circuit 31 (specified digital valuejudgment section) (hereinafter referred to as the NOR circuit) and aspecified voltage application transistor TN32 (specified voltageapplication section). The NOT/OR operation circuit 31 processes theincoming signals of the output signals d10-d13 output from each of theabove-mentioned latch circuits LC0-LC3. The specified voltageapplication transistor TN32 consisting of a Nch type Field-EffectTransistor (hereinafter referred to as FET) is individually connected toa voltage source applied to the control terminal (NOR gate) on one endof the current path to the specified voltage (Vbk,Vr) and the outputterminal of the relevant NOR circuit 31 on the opposite side to the loadcurrent supply line CL.

Here, the NOR circuit 31 as shown in FIG. 7, is configured with a seriescircuit and a parallel circuit. The series circuit is connected inseries to a plurality of Pch type FETs Tr41-Tr44 in between the highsupply voltage Vdd and an output contact Nout. The parallel circuit isconnected in parallel to a plurality of Nch FETs Tr45-Tr48 in betweenthe low supply voltage Vgnd (voltage to ground) and the output contactNout. Thus, the NOR circuit 31 is realized and it is feasible withcommon knowledge circuit arrangement to individually apply the outputsignals d10-d13 from each of the latch circuits LC0-LC3 to the controlterminals of each Pch and Nch FETs Tr41-Tr44 and Tr45-Tr48,respectively.

In the specified state setting section 30A which has such asconfiguration, the NOR circuit 31 judges whether or not all of thesignal levels of the output signals d10-d13 output from theabove-mentioned latch circuits LC0-LC3 are in the specified state set tozero (0). Only when in this specified state, the specified voltageapplication transistor TN32 performs an “ON” operation, and thespecified voltage (Vbk, Vr) is applied to the load current supply lineCL.

Therefore, according to the current generation circuit ISA of thisembodiment, along with the same effect as the first embodiment, thecurrent generation circuit performs drive control of the load from aplurality of digital signal bits. When all of the digital signal bits(output signals d10-d13) are set to zero (0), by isolating the currentoutput in the current generation section 20A, the signal levels of thecurrent supply source line CL will be in a high impedance state. Thisproblem which makes the operating state of the load unstable can besolved. Furthermore, with all of the digital signal bits (output signalsd10-d13) set to zero, by setting the signal levels of the load currentsupply line CL as a specified voltage the load can be driven by aspecified operating state. These functions are suitable for eliminatingabnormalities in the display, or application of the reset voltage whenapplied to the display device data driver of this current generationcircuit (described later in detail).

<<The Fourth Embodiment of the Current Generation Circuit>>

Next, the fourth embodiment of the current generation circuit related tothis invention will be explained with reference to the drawings.

FIG. 8 is an outline block diagram showing the fourth embodiment of thecurrent generation circuit in the display device related to thisinvention.

FIG. 9 is a circuit arrangement drawing showing an example of thedetailed configuration of the logic circuit applicable to the specifiedstate setting section of the current generation circuit in thisembodiment.

Here, concerning any configuration equivalent in the embodimentsmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

Although the case illustrated in the third embodiment mentioned above isconfigured (described as “current sinking method” for convenience) sothe load drive current ID is drawn in the direction of the currentgeneration circuit ISA from the load side connected to the currentgeneration circuit ISA, the fourth embodiment has a configuration(described as “current application method” for convenience) which flows(pours) the load drive current ID in the direction of the load from thecurrent generation circuit ISB side.

Specifically, as shown in FIG. 8, the current generation circuit ISBrelated to this embodiment has a configuration equivalent to the secondembodiment mentioned above comprising the signal latch section 10, thecurrent generation section 20B and a specified state setting section30B. The specified state setting section 30B applies the specifiedvoltage (Vbk, Vr) to the load current supply line CL only whenconnecting with the non-inverted output terminal OT of the latchcircuits LC0-LC3 to drive the load by a specified operating state.

Here, the current generator IRB is connected to the low supply voltageVgnd so reference current Iref flows in the current generator IRBdirection from the current generation section 20B side via the referencecurrent supply line Ls.

The specified state setting section 30B, as shown in FIG. 8, comprisesan OR operation circuit 33 and a specified voltage applicationtransistor TP34. The OR operation circuit 33 (hereinafter referred to asOR circuit as the digital value judgment section) which sets theincoming signals of the output signals d10-d13 output from each of theabove-mentioned latch circuits LC0-LC3. The specified voltageapplication transistor TP34 (specified voltage application section)consists of a Pch FET connected individually from the output of the ORcircuit 33 control terminal to a voltage source to which one end of thecurrent path applies the specified voltage Vbk and the other end side tothe current supply source line CL.

Here, OR circuit 33, for example as shown in FIG. 9A, is realized with acommon knowledge circuit configuration comprises a Not-AND gate 33 c(hereinafter referred to as a NAND circuit) with fanout from two inputNOR circuits 33 a and 33 b as an input. Two sets of two input NORcircuits 33 a and 33 b individually input the output signals d10-d11 andd12-d13 from each of the latch circuits LC0-LC3.

Specifically, as shown in FIG. 9B, such a common knowledge circuitarrangement applies the concept of two inputs in the NOR circuits 33 aand 33 b with Pch transistors Tr51 a-Tr52 a and Tr51 b-Tr52 bindividually connected in series in between the high supply voltage Vddand the output contacts Nota and Notb; Nch transistors Tr53 a-Tr54 a andTr53 b-Tr54 b are connected in parallel in between the low supplyvoltage Vgnd and the output contacts Nota and Notb; and the outputsignals d10-d13 of each of the latch circuits LC0-LC3 individuallyapplied to the control terminal of the Pch and Nch transistors Tr-51a-Tr54 a and Tr51 b-Tr54 b.

Also, a NAND circuit 33 c illustrated, as shown in FIG. 9B, utilizes acommon knowledge circuit arrangement to apply the concept of applyingindividually Pch transistors Tr55-Tr56 connected in parallel between thehigh supply voltage Vdd and the output contact Notc; Nch transistorsTr57-Tr58 connected in parallel between the low supply voltage Vgnd andthe output contact Notc; and fanout of each of the above-mentioned twoinput NOR circuits 33 a and 33 b (signal level of the output contactsNota and Notb) is applied to the control terminals of each Pch and Nchtransistors Tr55-Tr56 and Tr57-Tr58.

Also, in the specified state setting section 30B which has such aconfiguration, the OR circuit 33 judges whether or not all of the signaloutput signals d10-d13 output from the above-mentioned latch circuitsLC0-LC3 are in the specified state set to zero (0). The specifiedvoltage application transistor TP34 performs an “ON” operation only inthis specified state, and the specified voltage Vbk is applied to theload via the current supply source line CL.

Therefore, also in the current generation circuit ISB of thisembodiment, the same effect as the case of the third embodiment can beacquired in the current application method.

<<The Fifth Embodiment of the Current Generation Circuit>>

Next, the fifth embodiment of the current generation circuit related tothis invention will be explained with reference to the drawings.

As described later, in the case of applying the current generationcircuits in accordance with the present invention to the write-incurrent generation circuit clusters of the display device data driver,although configured so the plurality of current generation circuitsoperate in parallel and configured so the predetermined referencecurrent is supplied to each of the plurality of current generationcircuits, when the reference current is supplied in common to theplurality of current generation circuits from one constant current powersource, the value of the current supplied to each current generationcircuit becomes the current value into which the reference currentsupplied from the constant current power source was divided according tothe number of current generation circuits. At this time, the currentsupplied to each current generation circuit, where the componentcharacteristics (channel resistance and the like) of the referencecurrent transistors of the current generation section of each currentgeneration circuit are almost identical to each other, the currentsupplied to each current generation circuit as reference current becomesalmost uniform current (constant current) as it is divided almostequally. Therefore, equal drive current can be generated.

However, if a variation occurs in one another of the componentcharacteristics of each of the current generation circuit referencecurrent transistors (e.g., manufacturing differences or environmentalsurroundings, a change in the physical properties such as aging withtime and the like), because the current supplied to each currentgeneration circuit becomes that in which a variation divided unequallyhas reference current, the drive current generated will also producevariation.

Then, in addition to the configuration in each of the above-mentionedembodiment, this embodiment comprises a configuration which isintermittent in the supply of reference current in the currentgeneration circuit from a current generator. Accordingly, applying tothe data driver of the display device which describes the currentgeneration circuit related to this invention later, when operatingsimultaneously in parallel with a plurality of current generationcircuits, along with supplying selectively to each of the currentgeneration circuits reference current from a current generator, that isto say, it can be constituted so reference current can be supplied tothe current generation circuits one at a time. Therefore, each currentgeneration circuit generates drive current using the same referencecurrent and drive current variations can be controlled. When applied tothe display device, it can control variations in the luminositygradation of each display pixel and can acquire excellent display imagequality.

FIG. 10 is an outline block diagram showing one example of the currentgeneration section applied to the fifth embodiment of the currentgeneration circuit in the display device related to this invention.

FIG. 11 is a drawing showing an example of the detailed circuit of thecurrent generation section of the current generation circuit in thisembodiment.

FIG. 12 is an outline block diagram showing another example of thecurrent generation section applied to the current generation circuit inthis embodiment.

Here, concerning any configuration equivalent in the embodimentsmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

FIG. 10 illustrates a current generation section 20C as applied to thecurrent generation circuit related to this embodiment. For example, thecurrent generation section 20C has an almost equivalent circuitarrangement of the current generation section 20B (Reference FIG. 5)illustrated in the above second embodiment, along with being equippedwith a current mirror circuit 21C and a switching circuit 22C. Thecurrent mirror circuit 21C has a configuration with switching circuitsattached, which control (supply or cutoff) the supply state of thereference current Iref from the current supply source.

In particular, the current mirror circuit 21C is configured with Pchtransistors Tr61-Tr65 and switching circuits TS1 and TS2. A referencecurrent transistor Tr61 is connected in between contact Nm and thevoltage contact +V, along with the control terminal connected to contactNp. In addition, gradation current transistors Tr62-Tr65 areindividually connected in between the voltage contact +V and contactsNq, Nr, Ns and Nt, along with the control terminals connected in commonto contact Np. A capacitor C1 is connected in between theabove-mentioned contact Np and the voltage contact +V. Further, theswitching circuit TS1 is connected in between the current input INi andthe above-mentioned contact Nm, and the switching circuit TS2 isconnected in between the above-mentioned contact Nm and contact Np.

Resembling the current generation section 20B mentioned above, theswitching circuit 22C is configured with Pch transistors Tr66-Tr69applied in parallel connected in between each of the above-mentionedcontacts Nq, Nr, Ns and Nt and the current output contact OUTi, alongwith the output signals d10*-d13* output to each control terminal from aplurality of latch circuits.

Thus, also in this embodiment, the current mirror 21C is formed so thetransistor size of each gradation current transistor Tr62-Tr65 consistsof a predetermined ratio based on the reference current transistor Tr61,and the gradation current Idsq-Idst which flows to each current path isset up so the current value of each one is a different predeterminedratio as opposed to the current (reference current Iref) which flows tothe reference current transistor Tr61. Accordingly, in response to thesignal levels of output signals d10*-d13*, the specified transistorsTr66-Tr69 of the switching circuit section 22C perform an “ON”operation. The gradation currents Idsq, Idsr, Idss, Idst which have acurrent value twice the predetermined ratio of the reference currentIref flows via the gradation current transistors Tr62-Tr65. Randomgradation currents are selected and integrated from a plurality of thegradation currents Idsq, Idsr, Idss and Idst, the drive current ID isgenerated and output from the current output contact OUTi.

Further, the current mirror circuit 21C related to this embodiment isconfigured with the switching circuit TS1 formed between the currentinput contact INi and contact Nm, and the switching circuit TS2 formedbetween contact Nm and contact Np. The switching circuits TS1 and TS2perform setting control to correctly execute the “ON” and “OFF”operations. Thus, the switching circuits TS1 and TS2 are configured tosupply or cutoff the current path of the reference current Iref ofreference current transistor Tr61, as well as perform switching controlof the connection or cutoff between the current path of the referencecurrent transistor Tr61 and the control terminal.

Here, for example as shown in FIG. 11, specifically the switchingcircuits TS1 and TS2 can be configured with an Nch FET so the switchingcontrol of the “ON” and “OFF” state is performed by a single controlsignal rck (described later in detail). In the circuit arrangement shownin FIG. 11, by applying a high-level control signal rck, both theswitching circuits TS1 and TS2 perform an “ON” operation. Thus, thereference current Iref generated by the current generator is supplied tocontact Nm and contact Np, and performs an “ON” operation of thereference current transistor Tr61. Likewise, by applying a low-levelcontrol signal rck, both of the switching circuits TS1 and TS2 performan “OFF” operation and isolate supply of the reference current Iref tocontact Nm and contact Np, and performs an “OFF” operation of thereference current transistor Tr61.

Additionally, when applied to the data driver which describes aplurality of current generation circuits comprising a current generationsection 20C later in this embodiment, generation of the drive current ineach current generation circuit is addressed. By performing “ON” and“OFF” control selectively of switching circuits TS1 and TS2 formed ineach of current generation circuits; perform an “ON” operation only ofthe switching circuits TS1 and TS2 formed in any one current generationcircuit; and perform and “OFF” operation of the switching circuits TS1and TS2 formed in the other current generation circuits, it controls allat one time so the reference current Iref is supplied only to therelevant current generation circuit. Accordingly, as reference currentIref is supplied to the reference current transistors of only onecurrent generation circuit of the plurality of current generationcircuits, drive current is generated based on the present referencecurrent Iref.

Furthermore, the current generation circuit shown in this embodiment anda configuration which can realize the equivalent functions, for example,the current generation section 20D (current mirror circuit 21D) whichhas the circuit arrangement shown in FIG. 12 can also be applied. Inother words, the current mirror circuit 21D shown in FIG. 12, inaddition to the reference current transistor Tr61 and the gradationcurrent transistors Tr62-Tr65 which constitute a current mirror circuitequivalent to the current mirror circuit 21C as shown in FIG. 11, has aconfiguration comprising a switching circuit TS3 connected in betweenthe current input contact INi and the current path of the referencecurrent transistor Tr61, and a switching circuit TS4 connected betweenthe current input contact INi and the control terminal (contact Np) ofthe reference current transistor Tr61.

Thus, the current mirror circuit 21D, along with the current mirrorcircuit 21C shown in FIG. 11, the above-mentioned switching circuits TS3and TS4 are configured so the switching control supply or cutoff to thereference current Iref current path and control terminal of thereference current transistor Tr61 may be performed.

In addition, in this embodiment although the circuit arrangementattached the switching circuits TS1-TS2 or TS3-TS4 to a configurationcomprises the current generation section 20B shown in FIG. 5, that is,the current mirror circuit 21B and the switching circuit 22B which areconfigured with Pch transistors is shown, this invention is not limitedto this type only. Thus, the current generation section 20A shown inFIG. 3, it is possible to have a circuit arrangement with attachedswitching circuits TS1-TS2 or TS3-TS4 in a configuration comprises thecurrent mirror circuit 21A and the switching circuit 22A consisting ofNch transistors. The switching circuits TS1-TS2 or TS3-TS4 are notlimited to Nch transistors as Pch transistors may also be used, as wellas perform switching control of the “ON” and “OFF” states with signalsof the opposite polarity of the above-mentioned control signal rck. Adetailed configuration of a current generation circuit comprising thesecurrent generation sections is shown in the configuration of the displaydevice data driver described later.

2. Display Device

A current generation circuit which has such a composition and functionsmentioned above is applicable as a favorable pixel driver circuit whichforms the drive control device of a display device or the display pixelsof a display panel. A display device comprising such a currentgeneration circuit related to the present invention will be described indetail below.

First, an embodiment in the case of applying a current generationcircuit related to this invention to the drive control device of adisplay device will be explained with reference to the drawings.

<<The First Embodiment of the Display Device>>

FIG. 13 is an outline block diagram showing the first embodiment of thedisplay device related to this invention.

FIG. 14 is an outline block diagram showing an example of theconfiguration of the display panel applied to the display device relatedto this embodiment.

FIG. 15 is an outline block diagram showing another example of theconfiguration of the display device related to this embodiment.

Here, explanation will be made to the configuration comprising displaypixels corresponding to an active-matrix display panel. Also, in thisembodiment, explanation will be made to the adopted configuration of thecurrent sinking method.

As shown in FIGS. 13-14, a display device 100A related to thisembodiment, in brief, comprises a display panel 110 consisting of aplurality of display pixels EM arranged in a matrix shape; a scanningdriver 120A (scanning driver circuit) connected to the scanning linesSL; a data driver 130A (signal driver circuit) connected to the signallines DL; a voltage driver 140 connected to the voltage lines VLconnected in common for every display pixel cluster arranged in the linewriting direction of the display panel 110A and arranged in parallel tothe above-mentioned scanning lines SL; a system controller 150 outputwhich generates various control signals to control the operating stateof the scanning driver 120A, the data driver 130A and the voltage driver140; and a display signal generation circuit 160 which generates displaydata, the timing signal and the like based on a video signal suppliedexternally from the display device 100A.

Hereinafter, explanation of each of the above-mentioned constructionwill be explained in detail.

<<Display Panel>>

Specifically, the display panel 110A as shown FIG. 14, has a pluralityof scanning lines SL and voltage lines VL, a plurality of the signallines DL (data lines) and a plurality of display pixels EM. Theplurality of scanning lines SL is arranged in parallel with each other.The plurality of the signal lines DL are arranged to intersectperpendicularly with the scanning lines SL and the voltage lines VL. Theplurality of display pixels EM are arranged close to the intersectingpoint of each line that intersects perpendicularly. (A configurationwhich forms pixel driver circuits DCx and organic EL devices describedlater.)

The display pixels EM, for example, consist of having pixel drivercircuits DCx and optical elements. The pixel driver circuits DCx controlthe write-in operation of the write-in current Ipix and a lightgeneration operation in each of the display pixels EM, based on thescanning signal Vsel applied via the scanning lines SL from the scanningdriver 120, and the write-in current Ipix (drive current) supplied viathe signal lines DL from the data driver 130A, and the power supplyvoltage Vsc applied via the voltage lines VL from the voltage driver140. The optical elements consist of light emitting elements, which areuniversally known organic EL devices OEL as the current drive typeoptical elements by which the light generation luminosity (also known asbrightness or intensity) is controlled according to the current value ofthe light generation drive current supplied from the pixel drivercircuits DCx. In this embodiment, although the case where the organic ELdevices OEL are applied as the current drive type light emittingelements, light emitting elements beside light emitting diodes and thelike may be applied.

Here, the pixel driver circuits DCx, briefly, have the functions to takein write-in current Ipix in response to the display data selection stateand hold as the voltage level, which is controlled according to theselection/non-selection state of each of the display pixels EM inresponse to the scanning signal Vsel; to supply light generation drivecurrent to the organic electroluminescent (EL) devices OEL (hereinafterreferred to as organic EL devices) (optical elements) according to thevoltage level held (above-mentioned) in the non-selection state; and tomaintain operation to emit light by predetermined luminosity gradation.In addition, explanation of a possible example circuit arrangementapplicable to the pixel driver circuits DCx will be described later.

<<Scanning Driver>>

The scanning driver 120A sets the selection state for each line of thedisplay pixel clusters by sequentially applying the scanning signal Vselto each scanning lines SL at predetermined timing, based on the scanningcontrol signal supplied from the system controller 150; supplies thewrite-in current Ipix based on the display data to each of the signallines DL by the data driver 130A; and controls the write ofpredetermined write-in current in each display pixel.

Specifically, the scanning driver 120A shown in FIG. 14 is formed by ashift block SB consisting of a shift register and a buffer and has aplurality of steps. In this scanning driver 120, shift signals areoutput sequentially shift from the upper part to the lower part of thedisplay panel 110A by a shift register and are applied to each of thescanning lines SL as the scanning signal Vsel, which have apredetermined voltage level (selection level) via a buffer, based on ascanning control signal (scanning start signal SSTR, scanning clocksignal SCLK and the like) supplied from the system controller 150.

<<Data Driver>>

The data driver 130A takes in and holds the display data which comprisesa plurality of digital signal bits supplied from the display signalgeneration circuit 160, based on the data control signals supplied fromthe system controller 150; generates a write-in current Ipix which has acurrent value according to the relevant display data; and controls thewrite-in current supply to each of the signal lines DL simultaneouslyand parallel. Thus, in the data driver 130A related to this embodiment,the current generation circuit of each embodiment mentioned above isfavorably compatible. A detailed circuit arrangement example of the datadriver 130A and its drive control operation will be described later.

<<Voltage Driver>>

The voltage driver 140 draws in the predetermined write-in current Ipixbased on the display data and synchronizing with the timing sets theselection state for each line of every display pixel cluster from thescanning driver 120 based on a voltage control signal supplied from thesystem controller 150, by applying the power supply voltage Vscselection level (For instance, a low-level set less than the groundsupply (voltage to ground)) to the voltage lines VL, for example, in thedirection of the data driver 130A via the display pixels EM (pixeldriver circuits DCx) from the voltage lines VL. Meanwhile, the voltagedriver 140 controls the flow of the light generation drive currentequivalent to the above-mentioned write-in current Ipix in the directionof the organic EL devices OEL (optical elements) via the display pixelsEM (pixel driver circuits DCx) from the voltage lines VL, synchronizingwith the timing sets of the non-selection state for each line of everydisplay pixel cluster from the scanning driver 120 by applying the powersupply voltage Vs. non-selection level (For example, a high-level) tothe voltage lines VL.

Specifically, the voltage driver 140 shown in FIG. 14 is formed by ashift block SB consisting of a shift register and a buffer like thescanning driver 120A mentioned above corresponding to each and every oneof the voltage lines VL, has a plurality of steps and supplied from thesystem controller 150. In this voltage driver 140, based on a voltagecontrol signal (a power start signal VSTR, a voltage clock signal VCLKand the like) which synchronizes with the above-mention scanning controlsignal, shift signals are output sequentially shift from the upper partto the lower part of the display panel 110A from a shift register andapplied to each of the voltage lines VL as the power supply voltage Vsc,which has a predetermined voltage level via a buffer.

<<System Controller>>

The system controller 150 receives each of at least the scanning driver120A, the data driver 130A and the voltage driver 140 according to thetiming signal supplied from the display signal generation circuit 160described later. By generating and outputting the scanning controlsignal (the scanning start signal SSTR, the scanning clock signal SCLKand the like which were mentioned above), the data control signals and avoltage control signal (the power start signal VSTR, the voltage clocksignal VCLK and the like which were mentioned above), each driveroperates to predetermined timing. The power supply voltage Vsc, thescanning signal Vsel and the write-in current Ipix are made to output tothe display panel 110A; perform continuously predetermined drive controloperations in the pixel driver circuits DCx; and perform control to thedisplay panel 110A made to display predetermined image information basedon the video signal.

The system controller 150 generates and outputs the scanning controlsignal, the data control signals (the scanning start signal SSTR, thescanning clock signal SCLK; the sampling start signal STR and the shiftclock signal SFC and the like; the voltage control signal (the powerstart signal VSTR and the voltage clock signal VCLK and the like) toeach of at least the scanning driver 120A, the data driver 130A and thevoltage driver 140 according to the timing signal supplied from thedisplay signal generation circuit 160 described later. By generating andoutputting the above mentioned signals, the system controller 150performs each driver to operate at predetermined timing; to output thepower supply voltage Vsc, the scanning signal Vsel and the write-incurrent Ipix to the display panel 110A; to perform continuouslypredetermined drive control operations in the pixel driver circuits DCx;and to perform control to the display panel 110A made to displaypredetermined image information based on the video signal.

<<Display Signal Generation Circuit>>

The display signal generation circuit 160, for example, extracts theluminosity gradation signal component from the video signal suppliedfrom outside the display device 100A; supplies a luminosity gradationsignal component for every one line period (horizontal scanning period)of the display data panel 110A; and supplies the display data and thedata driver 130A, which is made up from a plurality of digital signalbits. Here, when the above-mentioned video signal contains the timingsignal component which specifies the display timing of image informationsuch as a television broadcasting signal (composite video signal), thedisplay signal generation circuit 160 has a function which extracts thetiming signal component supplied to the system controller 150 andanother function which extracts the above-mentioned luminosity gradationsignal component. In this case, the above-mentioned controller 150generates the above-mentioned scanning control signal, the data controlsignal and the voltage control signal supplied to the scanning driver120, the data driver 130A and the voltage driver 140 based on the timingsignal supplied from the display signal generation circuit 160.

In addition, although in this embodiment, as shown in FIG. 13 and FIG.14, a configuration which arranges individually the scanning driver 120Aand the voltage driver 140 as the driver attached on the periphery ofthe display panel 110A was explained, this invention is not limited tothis. For example, as mentioned above, since it operates based on anequivalent control signal (the scanning control signal and the voltagecontrol signal) which has synchronized timing, as shown in FIG. 15, thescanning driver 120A and the voltage driver 140 may be formed, forexample, so it has a function which supplies the power supply voltageVsc synchronizing the output timing with generation of the scanningsignal Vsel to the scanning driver 120B. According to such anarrangement, the configuration of the periphery circuit can besimplified and made space-saving.

Furthermore, the configuration of the display device as shown in FIGS.13-15, the pixel driver circuits DCx formed in each of the displaypixels EM form the display panel by performing setting control accordingto the status of the power supply voltage Vsc signal levels with thescanning signal Vsel described later (Reference FIG. 16). Althoughcorresponding to a situation whereby the circuit arrangement realizes apredetermined drive control operation, in order that this invention notbe limited to this, it will be described later (Reference FIG. 20). Forexample, the pixel driver circuit directly connected to the high supplyvoltage may have a circuit arrangement by which a regular constantvoltage level is applied and set to the display device shown in FIG. 13and FIG. 14 in this case. A configuration which does not have a voltagedriver 140 is also applicable.

<<Pixel Driver Circuit>>

Subsequently an example of the configuration of the pixel driver circuitas applied to each display pixel of the display panel mentioned abovewill be described.

FIG. 16 is a circuit arrangement drawing showing an example of oneconfiguration of the pixel driver circuit corresponding to the currentsinking method applicable to the display device related to thisembodiment.

In addition, the pixel driver circuit shown here only represents anexample applicable to the display device related to this invention.Needless to say, there can be other circuit arrangements having anequivalent operational function.

As shown in FIG. 16, the pixel driver circuits DCx related to thisexample case has a configuration an Nch transistor Tr71, an Nchtransistor Tr72, an Nch transistor Tr73 and a capacitor Cx. In the pixeldriver circuits DCx, near the intersecting point in which the scanninglines SL and the signal lines DL are arranged so these lines intersectat right angles with each other, the Nch transistor Tr71 is individuallyconnected by means of the source terminal to contact Nxa, the drainterminal to the voltage lines VL arranged in parallel with the scanninglines SL and the gate terminal to the scanning lines SL. An Nchtransistor Tr72 is individually connected by means of the gate terminalto the scanning lines SL, as well as the drain terminal and the sourceterminal is individually connected to the signal lines DL and contactNxb. An Nch transistor Tr73 is individually connected by means of thegate terminal to contact Nxa, and the drain terminal and source terminalindividually connected to the voltage lines VL and contact Nxb. Thecapacitor Cx is connected in between contact Nxa and Nxb.

Additionally, the organic EL devices OEL described earlier for lightgeneration luminosity are controlled by the light generation drivecurrent supplied from the pixel driver circuits DCx. The organic ELdevices OEL anode terminal is connected to contact Nxb of theabove-mentioned pixel driver circuit, and the cathode terminal isindividually connected to the low supply voltage Vgnd (voltage toground). Here, the capacitor Cx may be parasitic capacitance formed inbetween the gate-source of the Nch transistor Tr73, and a capacitativeelement (a capacitor) can be attached (added) separately in between thegate-source in addition to the parasitic capacitance.

Initially, the drive control operation of the organic EL devices OEL inthe pixel driver circuits DCx of such construction, in a write-inoperation period, while applying a high-level (selection level) scanningsignal Vsel to the scanning lines SL, the power supply voltage Vsc atthe same time applies a low-level to the voltage lines VL. Also,synchronizing with this timing, the pixel driver circuits DCx suppliesthe predetermined write-in current Ipix (equivalent to the drive currentID mentioned above) to the signal lines DL, which is required to performa light generation operation of the organic EL devices OEL byway ofpredetermined luminosity gradation. Here, negative polarity current issupplied as the write-in current Ipix and set up so the relevant currentis drawn in the direction of the data driver 130A via the signal linesDL from the side of the pixel driver circuits DCx (current sinkingmethod).

Accordingly, Nch transistors Tr71 and Tr72 which constitute the pixeldriver circuits DCx perform an “ON” operation. At the same time, alow-level of the power supply voltage Vsc is applied to contact Nxa(Namely, the gate terminal of the Nch transistor Tr73 and one end sideof the capacitor Cx), along with a low supply voltage level applied tocontact Nxb (Namely, the source terminal side of the Nch transistor Tr73and the other end side of the capacitor Cx) rather than a low-level ofthe power supply voltage Vsc via the Nch transistor Tr72 by the drawingin operation of the write-in current Ipix.

In this way, when a voltage potential difference occurs between thecontacts Nxa and Nxb (between the gate-source of the Nch transistorTr73), Nch transistor Tr73 performs an “ON” operation and the write-inoperating current according to the write-in current Ipix flows in thesignal lines DL direction via Nch transistor Tr73, contact Nxb and Nchtransistor Tr72 from the voltage lines VL (Reference FIG. 19 describedlater).

At this time, the electric charge corresponding to the voltage potentialdifference produced between the contacts Nxa and Nxb is stored incapacitor Cx, and is held as the voltage component (the capacitorcharges). Also, at this time since the supply applied to the anodeterminal (contact Nxb) of the organic EL device OEL becomes lower thanthe supply (voltage to ground) of the cathode terminal, reverse-biasvoltage is applied to the organic EL devices OEL. The light generationdrive current does not flow into the organic EL devices OEL, and lightgeneration is not performed.

Subsequently, in the light generation operation period, at the same timeit applies a low-level (non-selection level) scanning signal Vsel to thescanning lines SL, a high-level of the power supply voltage Vsc isapplied to the voltage lines VL. Also, synchronizing with this timing,the drawing in operation of the write-in current Ipix (Namely, write-incontrol current) is suspended.

Accordingly, since application of the voltage level resulting from thedrawing in operation of the write-in current Ipix to contact Nxb isinterrupted (shut down) while Nch transistors Tr71 and Tr72 perform an“OFF” operation, application of the power supply voltage Vsc to contactNxa is accordingly interrupted. The capacitor Cx then holds the electriccharge stored in the write-in operation mentioned above.

In this way, when capacitor Cx holds the charge voltage at the time ofthe write-in operation, the voltage potential difference between contactNxa and Nxb (between gate-source of the Nch transistor Tr73) will beheld, and Nch transistor Tr73 maintains an “ON” state. Also, because thepower supply voltage Vsc which has a voltage level higher than thevoltage to ground is applied to the voltage lines VL, the supply appliedto the anode terminal (contact Nxb) of the organic EL devices OELbecomes higher than the supply (voltage to ground) of the cathodeterminal.

Therefore, the light generation drive current flows into the organic ELdevices OEL in the forward-bias direction via Nch transistor Tr73 andcontact Nxb from the voltage lines VL, and the organic EL devices OELemit light by predetermined luminosity gradation. Here, since thevoltage potential difference (charge voltage) held by the capacitor Cxis equivalent to the voltage potential difference when flowing in thewrite-in operating current to Nch transistor Tr73 at the time of theabove-mentioned write-in operation, the light generation drive currentwhich flows to the organic EL devices OEL will have the current valueequivalent to the above-mentioned operating current. Accordingly, in thelight generation operation period, based on the voltage component inresponse to the predetermined light generation state (luminositygradation) written in the write-in operation period, the lightgeneration drive current will be supplied continuously and the organicEL devices OEL continue operation and emit light by the desiredluminosity gradation (Reference FIG. 19 described later). In this way,in the pixel driver circuit related to this embodiment, Nch transistorTr73 has the function as the transistor for light generation drive.

<<The First Embodiment of the Data Driver>>

Subsequently, the first embodiment of the data driver applied to thedisplay device related to this invention will be explained. The currentgeneration circuit of each of the above-mentioned embodiment is formedindividually in each signal line, and the data driver related to thisembodiment is constituted so the supplied reference current has aconstant value via a common current supply source line from a singlecurrent generator for example, as opposed to each current generationcircuit.

FIG. 17 is a circuit arrangement drawing showing the configuration ofthe first embodiment of the data driver in the display device concerningthis invention.

Here, an explanation will be provided matching the configuration of thecurrent generation circuit mentioned above. Furthermore, with referenceto any configuration equivalent in each embodiment mentioned above, thesame or equivalent nomenclature is appended and hereinafter theexplanation is simplified or omitted from the description.

As shown in FIG. 17 for example, the data driver 130A related to thisembodiment has a configuration which has a shift register circuit 131Awhich outputs sequentially the shift signals SR1, SR2, SR3 . . .(equivalent to the timing control signal CLK mentioned above) topredetermined timing, while shifting a sampling start signal STR basedon a shift clock signal SFC supplied as data control signal from thesystem controller 150; a write-in current generation circuit cluster132A which takes in sequentially the display data d0-dk (Here,equivalent to the digital signals d0-d3 mentioned above which are set tok=3 for convenience of explanation) in one line periods suppliedsequentially from the display signal generation circuit 160 based on thetiming input of the shift signals SR1, SR2, SR3 . . . from the shiftregister circuit 131A, generates the write-in current Ipix in responseto the light generation luminosity in each of the display pixels EM, andsupplied via each of the signal lines DL1, DL2, DL3, A common referencecurrent supply line Ls which regularly supplies the reference currentIref that has a constant current value to each of the write-in currentgeneration circuits ILA1, ILA2, ILA3 . . . , which form the write-incurrent generation circuit cluster 132A. The reference current Iref fromthe current generator IR (equivalent to the current generator IRAmentioned above) is formed externally of data driver 130A. Here, theconfiguration of the current generation circuit ILA of the firstembodiment mentioned above is applied to each of the write-in currentgeneration circuits ILA1, ILA2, ILA3 . . . , which form the write-incurrent generation circuit cluster 132A, provided with the signal latchcircuits 101, 102, 103 . . . (equivalent to the signal latch section 10mentioned above) and the current generation circuits 201A, 202A, 203A, .. . (equivalent to the current generation section 20A mentioned above).

<<Drive Control Method>>

Next, the drive control method of the display device which has theconfiguration mentioned above will be explained with reference to thedrawings.

FIG. 18 is a timing chart which shows an example of the drive controloperation of the data driver in this embodiment.

FIG. 19 is a timing chart which shows an example of the drive controloperation of the display panel in this embodiment.

Here, in addition to the configuration shown in FIG. 17, explanationwill accordingly refer to the configuration of the current generationcircuit shown in FIG. 1 and FIG. 3.

Initially, the drive control operation in the data driver 130A performsa signals holding operation which takes in the display data d0-d3supplied from the display signal generation circuit 160 to the signallatch circuits 101, 102, 103 . . . formed in the write-in currentgeneration circuits ILA1, ILA2, ILA3 . . . mentioned above and holds thedisplay data d0-d3 during a fixed period; and performs by setting thecurrent generation supply operation which generates the write-in currentIpix according to the above-mentioned display data d0-d3 that issupplied to each display pixel via each of the signal lines DL1, DL2,DL3 . . . , based on the holding signals d10-d13, d20-d23, d30-d33, ofthe display data d0-d3 taken in by the signals holding operation fromthe current generation circuits 201A, 202A, 203A, . . . formed in thewrite-in current generation circuits ILA1, ILA2, ILA3 . . . .

Here, in the signals holding operation, as shown in FIG. 18, based onthe shift signals SR1, SR2, SR3, . . . which are output sequentiallyfrom the shift register circuit 131A, the operation takes insequentially the display data d0-d3 which changes in response to eachline of display pixels EM (Namely, each of the signal lines DL1, DL2,DL3, . . . ) from each of the above-mentioned signal latch circuits 101,102, 103 . . . and performed continuously in one line periods. Thedisplay data d0-d3 are taken in sequentially from the signal latchcircuits 101, 102, 103, . . . and after a fixed period (The periodfollowing shift signals SR1, SR2, SR3, . . . until output.), the holdingsignals d10-d13, d20-d23, d30-d33, . . . are output to the currentgeneration circuits 201A, 202A, 203A, . . . .

Additionally, in the current generation supply operation, as shown inFIG. 18, based on the holding signals d10-d13, d20-d23, d30-d33, . . .the “ON/OFF” state of a plurality of switching transistors (transistorsTr26-Tr29 shown in FIG. 3) formed in each of the current generationcircuits 201A, 202A, 203A, . . . is controlled. A composite current ofthe gradation current, that flows into the gradation current transistors(transistors Tr22-Tr25 shown in FIG. 3) connected to a switchingtransistor which performs an “ON” operation, is supplied sequentiallyvia each of the signal lines DL1, DL2, DL3, . . . as the write-incurrent Ipix.

Here, the write-in current Ipix is controlled to all the signal linesDL1, DL2, DL3, . . . supplied simultaneously in parallel for at least afixed period.

In addition, as mentioned above in this embodiment, a plurality ofgradation currents are generated which have a current value of apredetermined ratio (For example, 2^(n); n=0, 1, 2, 3, . . . ) from thespecified transistor size established in advance to the referencecurrent Iref. Based on the above-mentioned holding signals,predetermined gradation currents are selected and integrated in responseto the “ON/OFF” operation of the switching transistors. Negativepolarity write-in current Ipix is generated in response to the lightgeneration luminosity in each of the display pixels EM, and the write-incurrent Ipix flows so it may be drawn in the direction of the datadriver 130A from the signal lines DL1, DL2, DL3, . . . side.

Also, in the data driver related to this embodiment, as shown in FIG.17, has a configuration of a plurality of the write-in currentgeneration circuits ILA1, ILA2, ILA3 . . . connected in parallel towardto a common reference current supply line Ls supplied by the referencecurrent Iref which has a constant current value from the currentgenerator IR. As shown in FIG. 18 in each of the current generationcircuits ILA1, ILA2, ILA3 . . . , because the write-in current Ipix toeach of the signal lines DL1, DL2, DL3, . . . is generatedsimultaneously and parallel based on the display data d0-d3, the currentsupplied to each of the current generation circuits ILA1, ILA2, ILA3 . .. via the reference current supply line Ls is not the reference currentIref itself from the current generator IR. Instead, corresponding to thenumber of write-in current generation circuits (equivalent to the numberof signal lines arranged in the display panel 110A; for example, mlines) that operate simultaneously and parallel as mentioned above,current which has a current value (Iref/m) divided almost equally issupplied.

Furthermore, the drive control operation in the display panel 110A, asshown in FIG. 19, sets a one cycle scanning period Tsc (one scanninginterval) as one cycle which displays the desired image information onone screen of the display panel 110A; selects the display pixel clustersconnected to the specified scanning lines within this one cycle scanningperiod Tsc; a write-in operation period (selection period) Tsc writes inthe write-in current Ipix in response to the display data supplied fromthe data driver 130A and is held as the signal level; supplies theorganic EL devices OEL (optical elements) the light generation currentin response to the above-mentioned display data based on the held signallevel; establishes the light generation operation period Tnse(non-selection period of the display pixels EM) which performs a lightgeneration operation by way of predetermined luminosity gradation(Tsc=Tse+Tnse); and performs drive control equivalent to the pixeldriver circuits DCx mentioned above in each operation period. Here, thewrite-in operation period Tse is set for every line is set up so a timeoverlap does not occur with one another. Also, the write-in operationperiod Tse is at least set as a period comprising a fixed period whichsupplies in parallel the write-in current Ipix to each signal line inthe current generation supply operation of the above-mentioned datadriver 130A.

To be exact, the write-in operation period Tse to the display panel, asshown in FIG. 19, performs the operation to instantly hold the write-incurrent Ipix as the voltage component supplied in parallel to each ofthe signal lines DL by the data driver 130A by scanning on apredetermined signal levels of the scanning lines SL and the voltagelines VL to the display pixels EM of a specified line (the i-th line)from the scanning driver 120 and the voltage driver 140. In a subsequentlight generation operation period Tnse, the light generation operationis continued by luminosity gradation according to the display data bycontinuously supplying the light generation drive current to the organicEL devices OEL (optical elements) based on the voltage component heldduring the above-mentioned write-in operation.

As shown in FIG. 19, by performing repeatedly in sequence such a seriesof drive control operations on each and every line of the display pixelclusters that constitute the display panel 110A, the display data of thedisplay panel for one screen is written in, each of the display pixelsEM emit light by predetermined luminosity gradation and the desiredimage information is displayed.

Consequently, in the data driver 130A and the display device 100Arelated to this embodiment, the write-in current Ipix is supplied tospecified lines of the display pixel clusters via each of the signallines DL in the data driver 130A and the display device 100A related tothis embodiment. Since it is generated from each of the write-in currentgeneration circuits ILA1, ILA2, ILA3 . . . based on the referencecurrent Iref (In detail, the current which is the reference current Irefequally divided by the number of the write-in current generationcircuits.) supplied in common via the reference current lines Ls fromthe current generator IR according to the display data d0-d3 (or thewrite-in current Ipix) supplied to each of the write-in currentgeneration circuits ILA1, ILA2, ILA3 . . . , the current value does notfluctuate. The limitations of operation resulting from the electricalcharge and discharge process of the reference current supply line Ls canbe alleviated. Furthermore, significant enhancement in the operatingspeed of the data driver, the display response characteristics in thedisplay device, as well as the display image quality can be achievedwith distinctly improved performance.

Besides, the data driver (write-in current generation circuit), incontrast to the reference current transistors into which theabove-mentioned reference current flows, the channel width of aplurality of gradation current transistors that have a circuitarrangement with a current mirror circuit are set so each consists of apredetermined ratio (For example, 2^(n) gradation) Since the write-incurrent flows to a plurality of gradation currents set to a 2^(n)current value, display data is generable by integrating these accordingto their status. With a relatively simple circuit arrangement, write-incurrent can be generated using analog current that has a suitablecurrent value corresponding to the display data (a plurality of digitalsignal bits), as well as a light generation operation of the displaypixels EM can be performed by the proper luminosity gradation.

<<The Second Embodiment of the Data Driver>>

Subsequently, the second embodiment of the data driver applied to thedisplay device related to this invention will be explained.

Although the data driver in the first embodiment of the above-mentionedis configured with a circuit arrangement corresponding to the currentsinking method whereby write-in current is drawn in the direction of thedata driver from the display pixels, this invention is not limited tothis and conversely may be configured with a circuit arrangement of thecurrent application method whereby supplied write-in current flows(pours) in the direction of the display pixels from the data driver.

The data driver concerning this embodiment is configured with a circuitarrangement of the current application method.

FIG. 20 is a circuit arrangement drawing showing the configuration ofthe second embodiment of the data driver in the display device relatedto this invention.

Here, an explanation will be provided matching the configuration of thecurrent generation circuit mentioned above. Furthermore, with referenceto any configuration equivalent in each embodiment mentioned above, thesame or equivalent nomenclature is appended and hereinafter theexplanation is simplified or omitted from the description.

A data driver 130B related to this embodiment, for example, as shown inFIG. 20, has a configuration formed a shift register circuit 131B whichoutputs sequentially the shift signals SR1, SR2, SR3, . . . based on thedata control signals (a shift clock signal SFC and a sampling startsignal STR) is supplied from the system controller 150; a write-incurrent generation circuit cluster 132B which takes in sequentially thedisplay data d0-d3 for one line period supplied sequentially from thedisplay signal generation circuit 160 based on the timing input of theappropriate shift signals SR1, SR2, SR3, . . . generates the write-incurrent Ipix according to the light generation luminosity in each of thedisplay pixels EM, and supplies them via each of the signal lines DL1,DL2, DL3, . . . ; and a common reference current supply line Ls drawsout regularly the reference current Iref that has a current value fromthe current generator IR (equivalent to the current generator IRBmentioned above) formed externally of data driver 130B. Here, each ofthe write-in current generation circuits ILB1, ILB2, ILB3, . . . formthe write-in current generation circuit cluster 132B, which is appliedto a configuration of the current generation circuit ILB of the secondembodiment mentioned above. Also, this configuration comprises thesignal latch circuits 101, 102, 103, . . . (equivalent to the signallatch section 10 mentioned above) and the current generation circuits201B, 202B, 203B, . . . (equivalent to the current generation section20B mentioned above).

The drive control operation of data driver 130B is the essentially thesame as that of the first drive control method (Reference FIGS. 18-19)of the display device illustrated in the embodiment mentioned above, andset to a signal holding operation. Based on the shift signals SR1, SR2,SR3, . . . output sequentially from the shift register 131B to each ofthe above-mentioned latch circuits 101, 102, 103, . . . , the operationtakes in sequentially the display data d0-d3 which changes in responseto each line of the display pixels EM (each of the signal lines DL1,DL2, DL3, . . . ) from each of the above-mentioned signal latch circuits101, 102, 103 . . . and performed continuously in one line periods. Theholding signals d10*-d13*, d20*-d23*, d30*-d33* . . . are equivalent toan inverted signal of a fixed period and the display data d0-d3, andoutput to the current generation circuits 201B, 202B, 203B, . . . .

In addition, the current generation supply operation, based on theholding signals d10*-d13, d20*-d23*, d30*-d33* . . . , selects andintegrates the predetermined gradation current from a plurality ofgradation currents which have a current value of a predetermined ratiospecified in advance to the reference current Iref drawn out from eachof the current generation circuits 201B, 202B, 203B, . . . ; generatesthe write-in current Ipix of positive polarity, which is suppliedsequentially so as to flow in the direction of the display pixels EM ofeach of the signal lines DL1, DL2, D3, . . . from the data driver 130Bside.

<<Pixel Driver Circuit>>

FIG. 21 is a circuit arrangement drawing showing an example of oneconfiguration of the pixel driver circuit corresponding to the currentapplication method applicable to the display device in this embodiment.

In addition, the shown pixel driver circuit is just one exampleapplicable to the display device concerning this embodiment. Needless tosay, there can be other circuit arrangements which have an equivalentoperational function.

As shown in FIG. 21, the pixel driver circuit DCy related to thisexample configuration comprises a Pch transistor Tr81, an Nch transistorTr82, a Pch transistor Tr83, an Nch transistor Tr84 and a capacitor Cy.The Pch transistor Tr81 drain terminal and source terminal areindividually connected to the voltage contact +V and the contact Nya;the gate terminal is connected to the scanning lines SL and near theintersecting point of the scanning lines SL and the signal lines DL. TheNch transistor Tr82 gate terminal is connected to the scanning lines SL,along with the drain terminal and source terminal each other connectedto the signal lines DL and contact Nya. The Pch transistor Tr83 gateterminal is connected to contact Nyb, along with the drain terminal andsource terminal each other connected to contact Nya and Nyc. The Nchtransistor Tr84 gate terminal is connected to the scanning lines SL,along with the drain terminal and source terminal each other connectedto contact Nyb and contact Nyc. Also, the capacitor Cy is connected inbetween contact Nya and contact Nyb. Here, the voltage contact +V isconnected to the voltage driver shown in the embodiment mentioned above,or a direct high supply voltage via a voltage line, and constant highsupply voltage is applied.

In addition, this example configuration comprises the organic EL devicesOEL with which light generation luminosity is controlled by the lightgeneration drive current supplied from such a pixel driver circuit DCy.The anode terminal is each other connected to contact Nyc of theabove-mentioned pixel driver circuit DCy, and the cathode terminal isconnected separately to the low supply voltage Vgnd. It is here, thecapacitor Cy may be parasitic capacitance formed in between thegate-source of the transistor Tr83, and a capacitative element (acapacitor) can be attached (added) separately in between the gate-sourcein addition to the parasitic capacitance.

The drive control operation of the organic EL devices OEL in the pixeldriver circuit DCy which has such a configuration, first, in thewrite-in operation period, supplies the write-in current Ipix forperforming a light generation operation of the organic EL devices OEL bypredetermined luminosity gradation to the signal lines DL synchronizingwith this timing while applying a high-level (selection level) scanningsignal Vsel to the scanning lines SL. Here, the write-in current Ipixsupplies positive polarity current set up so the relevant current flowsin the direction of the pixel driver circuit DCy via the signal lines DLfrom the data driver 130B side.

Accordingly, at the same time the transistors Tr82 and Tr84 which formthe pixel driver circuit DCy perform an “ON” operation, the transistorTr81 performs an “OFF” operation, and positive current is suppliedcorresponding to the write-in current Ipix supplied to the signal linesDL which is applied to contact Nya. Furthermore, as between contact Nyband contact Nyc connect, between the gate-source and between thesource-drain of the transistor Tr83 controls this electric potential. Bythis, a voltage potential difference according to the write-in currentoccurs in capacitor Cy (between contact Nya and contact Nyb). Theelectric charge corresponding to this voltage potential difference isaccumulated and held as the voltage component (charge).

Subsequently, in the light generation operation period, while applying alow-level (non-selection level) scanning signal Vsel to the scanninglines SL, it synchronizes with this timing to interrupt (turn off) thesupply of the write-in current Ipix. Consequently, capacitor Cy holdsthe electric charge accumulated in the write-in operation mentionedabove by intervening electrically between the transistors Tr82 and Tr84performing an “OFF” operation, the signal lines DL and contact Nya,together with between contact Nyb and contact Nyc.

In this way, when capacitor Cy holds the charge voltage at the time ofthe write-in operation, the voltage potential difference between contactNyb and contact Nyc (between the gate-source of transistor Tr83) will beheld, and the transistor Tr83 performs and “ON” operation. As a result,by application of the above-mentioned scanning signal Vsel (low-level),since the transistor Tr81 performs an “ON” operation simultaneously, thelight generation drive current responsive to the write-in current Ipixflows to the organic EL devices OEL via transistors Tr81 and Tr83 fromthe voltage contact +V (high supply voltage), and the organic EL devicesOEL emit light by predetermined luminosity gradation. In this way, inthe pixel driver circuit related to this embodiment, an Nch transistorTr83 will have the function as the transistor for the light generationdrive.

Accordingly, in the write-in operation period in the display panel 110Awhich has the pixel driver circuit (Reference FIG. 13) mentioned abovefor every line of display pixels EM, the above-mentioned write-incurrent Ipix is supplied via each of the signal lines DL1, DL2, DL3, . .. . The present write-in current Ipix is held as the voltage componentand set during a light generation operation. The light generation drivecurrent is supplied continuously to the organic EL devices OEL based onthe held voltage component. The light generation operation is continuedby the luminosity gradation corresponding to the display data d0-d3.

Therefore, as explained in this embodiment, the write-in currentsupplied to the display panel (display pixels EM) can in fact begenerated based on the current value of the reference current suppliedvia a common current supply source line. The current value supplied toeach of the write-in current generation circuits which form the datadriver does not fluctuate. Thus, limitations in the operating speedoriginating in the charge and discharge of the current supply sourceline can be alleviated, as well as the operating speed of the datadriver can be elevated.

<<The Third Embodiment of the Data Driver>>

Subsequently, the third embodiment of the data driver applied to thedisplay device mentioned above will be explained.

FIG. 22 is an outline block diagram showing an example of a currentgeneration circuit applied to the third embodiment of the data driver inthe display device concerning this invention.

FIG. 23 is an outline block diagram showing another example of thecurrent generation circuit applied to the data driver in thisembodiment.

The data driver in this third embodiment applies the current generationsection of the current generation circuit in the fifth embodiment shownin FIG. 11 to the current generation section of the current generationcircuit which forms the data driver of each of the write-in currentgeneration circuits while comprising a configuration equivalent to thedata driver of the second embodiment shown in FIG. 20.

Here, concerning any configuration equivalent in the embodimentsmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

A current generation circuit ILC configured with each of the write-incurrent generation circuits provided in the data driver related to thisembodiment, for example, as shown in FIG. 22, includes the signal latchsection 10 shown in FIG. 4 and the current generation section 20C shownin FIG. 11. Moreover, the current generation circuit ILC is configuredwith an operation setting circuit 70. The operation setting circuit 70comprises an inverter 72 which performs reversal processing of thepredetermined selection signal SEL supplied from the system controller150 and the like; a Pch transistor Tr71 applies an inversion signal(reversed state) of the selection signal SEL output via theabove-mentioned inverter 72 to a control terminal connected on the otherend side of the signal lines DL current path and to which the currentoutput OUTi is connected on one end side of the current path; a NANDcircuit 73 which performs input of the inverted output of the inverter72 and the shift signal SR from the shift register circuit 131; aninverter 74 which performs reversal processing of the fanout (NAND gate)of the NAND circuit 73; and lastly an inverter 75 which performs furtherreversal processing of the inverted output of the inverter 74.

In a current generation circuit ILC which has such a configuration, ifthe high-level selection signal SL is input, the transistor Tr71 formedin the operation setting circuit 70 performs an “ON” operation, thecurrent output contact OUTi of current generation section 20C will beconnected to the signal lines DL via the transistor Tr71, and thecurrent generation circuit will be set to a selection state.

Concurrently at the same time, a low-level timing control signal isinput to contact CK of each of the latch circuits LC0-LC3 that form thesignal latch section 10, which is uninvolved with the output timing ofthe shift signal SR, from the inverter 72 and the NAND circuit 73, andthe inverters 74 and 75; as well as a high-level timing control signalis input regularly to input contact CK*. The display data d0-d3 aretaken in and held in each of the latch circuits LC0-LC3, as well astiming to which the high-level control signal rck mentioned above isapplied. Subsequently, the reference current Iref is supplied to thecurrent generation section 20C, gradation currents according to thedisplay data d0-d3 are integrated, and the write-in current Ipixcorresponding to the light generation luminosity in each of the displaypixels EM is generated. Accordingly, the write-in current Ipix based onthe display data d0-d3 generated to which timing is applied selectivelyby the control signal rck mentioned above in each of the currentgenerations circuits ILC is supplied sequentially to each of the displaypixels EM via the signal lines DL.

On the other side, if a low-level of the selection signal SL is input,the transistor Tr71 will perform an “OFF” operation, the current outputcontact OUTi of the current generation section 20C will be separatedfrom the signal lines DL, and the current generation circuit ILC will beset as a non-selection state.

Instantaneously, the inverter 72 and NAND circuit 73 along with theinverters 74 and 75 respond to the output timing of the shift signal SR(high-level) to the input contact CK and input contact CK* of each ofthe latch circuits LC0-LC3. The timing control signal which has a signallevel of opposite polarity takes in and holds the display data d0-d3.Timing by the control signal rck mentioned above is applied and thewrite-in current Ipix is generated according to the display data d0-d3.Accordingly, although the write-in current Ipix is generated based onthe display data d0-d3, it will be in the state where the signal linesDL are not supplied.

The drive control operation in the data driver comprising such as thecurrent generation circuit ILC is similar to the drive control method(Reference FIG. 18) of the display device shown in the embodimentmentioned above, and set to a signal holding operation with the latchsection 10 formed in each of a plurality of current generation circuitsILC; set to a selection state based on the shift signals SR1, SR2, SR3 .. . which are output sequentially from the shift register circuit 131.The holding signals d10*-d13* are equivalent to an inversion signal ofdisplay data d0-d3 taken in sequentially for every line of display datad0-d3 and output to the current generation section 20C.

Furthermore, it is the timing by which the above-mentioned controlsignal rck is applied selectively (It does not become a high-levelsimultaneously.) to only the current generation circuit ILC in aplurality of current generation circuits ILC in the current generationsupply operation. The reference current Iref is supplied to the currentgeneration section 20C based on the holding signals d10*-d13*.Predetermined gradation currents are selected and integrated from aplurality of gradation currents which have a current value specified inadvance based on this reference current Iref, generated write-in currentIpix of regular polarity via each of the signal lines DL1, DL2, DL3 . .. is supplied sequentially so it flows in the direction of the displaypixels EM.

Therefore, according to the display device related to this embodiment,generation of the write-in current is addressed by supplying selectivelythe reference current Iref to each of the current generation circuitsILC formed corresponding to each of the signal lines DL1, DL2, DL3, . .. , by generating and integrating the gradation currents according tothe display data d0-d3 based on the reference current Iref. Because thewrite-in current has an equal and suitable current value which can besupplied to each of the display pixels EM, without being influenced byvariations in circuit characteristics between each of the currentgeneration circuits and the component characteristics of the activedevice transistors and the like, a favorable gradation display operationcan be realized and enhancement in the display image quality can beachieved.

In addition, when generating the write-in currents in this embodiment,the control signal rck performs switching control to set the switchingcircuits TS1-TS2 or TS3-TS4 supply state of the reference current Irefto each of the current generation circuits ILC (current generationsection 20C). Although this case applied the signal generated and outputto the system controller 150 was explained. This invention is notlimited to this in order to reduce the processing load in the systemcontroller and the like, and to simplify circuit arrangement. Forexample, using other control signals currently supplied for operationalcontrol in each current generation circuit ILC, you may constitute aconfiguration so the switching control of the above-mentioned switchingcircuits TS1-TS2 or TS3-TS4 may be performed.

For example, as shown in FIG. 23, the current generation circuit ILD andin the current generation circuit ILC in FIG. 22 mentioned above set ina configuration so it can supply the control signal rck for performingswitching control of the switching circuits TS1-TS2 and TS3-TS4 in thecurrent generation section 20C for inverted output (Namely, the timingcontrol signal input to the input contact CK of each of the latchcircuits LC0-LC3 configured to the signal latch section 10.) of theinverter 74 formed in the operation setting circuit 70 of the currentgeneration circuit ILC.

Namely, the timing (The timing of the shift signals SR1 and SR2 outputfrom the shift register circuit 131, and synchronizing the timing) basedon the timing control signal to input contacts CK and CK* of each of thelatch circuits LC0-LC3 as mentioned above, in each of the latch circuitsLC0-LC3 a signal holding operation which takes in and holds the displaydata d0-d3 is performed and, a high-level control signal rck timing isapplied on the other side. The current generation supply operation isperformed which generates the write-in current Ipix according to thedisplay data d0-d3 and the reference current Iref is supplied to thecurrent generation section 20C. In applying the drive control method ofrepeating successively each of these operations simultaneously (inparallel), the timing control signal and the above-mentioned controlsignal rck supplied timing input to input contact CK of each of thelatch circuits LC0-LC3 will be set in sync. Thus, each operation iscontrollable using a single timing control signal.

Therefore, the circuit arrangement can be simplified while theprocessing load in the system controller and the like can be reduced;since drive control can be performed simultaneously using the existingcontrol signal supplied to each of the current generation circuits ILC,the signal holding operation in the signal latch section 10 and thecurrent generation supply operation in the current generation section20C according to such a configuration.

In addition, in the current generation circuits ILC and ILD shown inFIG. 22 and FIG. 23, the current generation circuit ILB shown in FIG. 4and these circumstances, the write-in current generated by each of thecurrent generation circuits ILC and ILD, although it has a circuitarrangement set up so it flows in the direction of the display pixels EMvia each signal line, this invention is not limited to this. It may havea circuit arrangement set similar to the current generation circuit ILAshown in FIG. 1 mentioned above so the above-mentioned write-in currentcan be drawn into the current generation circuits ILC and ILD via thesignal lines from each of the displays pixels sides.

<<The Fourth Embodiment of the Data Driver>>

Next, the fourth embodiment of the data driver applied to the displaydevice mentioned above will be explained.

As for the data driver related to this embodiment, briefly, in thisconfiguration two sets of write-in current generation circuits areformed in each of the signal lines. Each set of the write-in currentgeneration circuits to predetermined operation timing perform taking inof the display data, holding, generation of the write-in current and thesupply operation are performed complementarily and successively. Also,when each of the write-in current generation circuits comprises the sameconfiguration as the current generation circuit in the third embodimentof the current generation circuit, each of the write-in currentgeneration circuits supply specified voltage (black display voltage) tothe signal lines, thereby each has a specified state setting section andthe display data becomes a specified value accordingly. Here, in thisembodiment, positive reference current which has a constant currentvalue from a single current generator is supplied to the write-incurrent generation circuit cluster.

FIG. 24 is a circuit arrangement drawing showing the configuration ofthe fourth embodiment of the data driver in the display device relatedto this invention.

FIG. 25 is a circuit arrangement drawing showing one example of thewrite-in current generation circuit applied to the data driver in thisembodiment.

FIG. 26 is a circuit arrangement drawing showing one example of theinverted latch circuit applied to the data driver in this embodiment andthe selection setting circuit.

Here, the explanation matches with the configuration of the currentgeneration circuit mentioned above. Here, concerning any configurationequivalent in the embodiments mentioned above, the same or equivalentnomenclature is appended and the explanation is simplified or omittedfrom the description.

The data driver 130C related to this embodiment, for example as shown inFIG. 24, is configured with an inverted latch circuit 133A whichgenerates a non-inverted clock signal CK1 and an inverted clock signalCK2 based on the shift clock signal SFC supplied as the data controlsignal from the system controller 150; a shift register 134A whichoutputs sequentially the shift signals SR1, SR2, SR3 . . . (equivalentto the timing control signal CLK mentioned above) to predeterminedtiming, while shifting sampling start signal STR based on thenon-inverted clock signal CK1 and the inverted clock signal CK2; twosets of the write-in current generation circuit clusters 135A and 135Bwhich supply (drawn) via each of the signal lines DL1, DL2, . . . takein sequentially the display data d0-dk (Here, these are equivalent tothe digital signals d0-d3 which are set to k=3 for convenience andmentioned above.) in one line periods supplied sequentially from thedisplay signal generation circuit 160, and generate the write-in Ipixcorresponding to the light generation luminosity in each of the displaypixels EM; a selection setting circuit 136A outputs the selectionsetpoint signal (The non-inverted signal SLa and the inversion signalSLb of the switching control signal SEL) for operating selectivelyeither of the above-mentioned write-in current generation circuitclusters 135A and 135B, based on the switching control signal SELsupplied as the data control signal from the system controller 150.

Here, two sets of write-in current generation circuit clusters 135A and135B are configured at least so the reference current Iref input incommon has a constant current value regularly supplied from the currentgenerator IR (equivalent to the current generator IRA mentioned above)and the display data d0-dk supplied from the display signal generationcircuit 160.

Two sets of the write-in current generation circuit clusters 135A and135B have a configuration each comprising a plurality of write-incurrent generation circuits ISC1, ISC2, . . . and ISD1, ISD2, . . . .Each of the write-in current generation circuits ISC1, ISC2, . . . andISD1, ISD2, . . . shown in FIG. 25 corresponds to the current generationcircuit ISA (Hereinafter referred to as the write-in current generationcircuit ISx) in the third embodiment of the current generation circuitshown in FIG. 6, and is configured with a signal latch section 10 xwhich is equivalent to the configuration in the third embodiment of thecurrent generation circuit, and in addition to a current generationsection 20 x; a specified state setting section 30 x; and an operationsetting circuit 40 x to set selectively an operating state of eachwrite-in current generation circuits ISx based on the switching controlsignal SEL.

Here, since the signal latch section 10 x, the current generationsection 20 x and the specified state setting section 30 x are equivalentto the signal latch section 10 each shown in FIG. 6, the currentgeneration section 20A and the specified state setting section 30A areomitted from this section of the detailed description.

The operation setting circuit 40 x, for example, as shown in FIG. 25,has a configuration comprising an Nch transistor TN41 formed in thecurrent path to the signal lines DL and the selection setpoint signalfrom (the non-inverted signal SLa or the inverted signal SLb) selectionsetting circuit 136A applied to the control terminal. An inverter 42performs reversal processing of the selection setpoint signal. A NANDcircuit 43 performs input of the shift signal SR (SR1, SR2, . . . ) fromthe shift register 134A and inverted output of the inverter 42. Aninverter 44 performs reversal processing of the fanout of the NANDcircuit 43, and an inverter 45 performs reversal processing further theinverted output of the inverter 44.

In the write-in current generation circuit ISx which has such aconfiguration, if a high-level selection setpoint signal (A controlsignal which sets the write-in current generation circuit into aselection state) is input from the selection setting circuit 136A, theNch transistor TN41 formed in the operation setting circuit 40 x willperform an “ON” operation. The current output contact OUTi of thecurrent generation section 20 x is connected to the signal lines DL viathe Nch transistor TN41. Simultaneously at this time, a low-level timingcontrol signal to signal latch section 10 x input contact CK notinvolved with the output timing of the shift signal SR from the inverter42, the NAND circuit 43 and the inverters 44 and 45, and also ahigh-level timing control signal is input regularly to input contactCK*. The display data d0-d3 are taken in, and the write-in current Ipixaccording to the display data d0-d3 is generated by the currentgeneration section 20 x.

When display data d0-d3 are all set to zero (0), at the same time thewrite-in current Ipix in the current generation section 20 x isinterrupted (shut down) and a light generation operation (for example,black display operation) in the specified state of the display pixels EMis performed. The specified voltage vbk (black display voltage) inresponse to a black display operation to output contact OUTi current ofthe current generation section 20 x by the specified state settingsection 30 x is applied.

Accordingly, in an ordinary gradation display operation excluding ablack display state, the write-in current Ipix generated, based on thedisplay data d0-d3, is supplied to the display pixels EM via the signallines DL. A predetermined specified voltage Vbk (black display voltage)is applied to the signal lines DL, while shutting down the supply of theabove-mentioned write-in current Ipix at the time of a black displayoperation.

Conversely, if a low level selection setpoint signal (a control signalwhich sets the write-in current generation circuit as the non-selectionstate) is input from the selection setting circuit 136A, the Nchtransistor TN41 will perform an “OFF” operation, and the current outputcontact OUTi of the current generation section 20 x will be isolated(separated) from the signal lines DL.

Simultaneously at this time, corresponding to the output timing of theshift signal SR, a timing control signal which has a complementary(matching) signal level is input to the input contact CK and inputcontact CK* of the signal latch section 10 x corresponding to the outputtiming of the shift signal SR from the inverter 42 and the NAND circuit43, along to the inverters 44 and 45, taking in the display data d0-d3,held and the generation operation of the write-in current Ipix areperformed. Accordingly, although the write-in current Ipix is generatedbased on display data d0-d3, it will be in the state where the signallines DL are not supplied, and the write-in current generation circuitwill be essentially set into a non-selection state. Thus, from theselection setting circuit 136A described later, by setting appropriatelythe signal level of the selection setpoint signal (The non-invertedsignal SLa and the inversion signal SLb of the switching control signalSEL.) input to two sets of the write-in current generation circuitclusters 135A and 135B, the selection-state of either of the two sets ofthe write-in current generation circuit clusters 135A and 135B can beset into the selection state and the other can be set into thenon-selection state.

Moreover, the inverted latch circuit 133A and the selection settingcircuit 136A, briefly, has a circuit arrangement equivalent, forexample, as shown in FIGS. 26A and 26B, to apply a configurationcomprising multiple well-known inverter circuits (For example, acomplementary type transistor circuit as shown in FIG. 2).

Specifically, the inverted latch circuit 133A and the selection settingcircuit 136A, the shift clock signal SFC or the switching control signalSEL is input into the input contact INs (the input terminal of theinverted latch circuit 133A or the selection setting circuit 136A) of aninverter INV1 and the output contact of the inverter INV1 is connectedto the input contact of an inverter INV2. The output contact of theinverter INV2 is connected to the input contact of the inverter INV4.Also, the above-mentioned shift clock signal SFC or the switchingcontrol signal SEL is input into the input terminal of an inverter INV3and the output contact is connected to the input contact of an inverterINV5. While the output contact of the inverter INV4 is connected to theinput contact of the inverter INV5 and an inverter INV6, the outputcontact of the inverter INV5 is connected to the input contact of theinverter INV4 and an inverter INV7. Also, the output contact of theninverter INV6 is connected to a non-inverted output terminal OUTs of theinverted latch circuit 133A or the selection setting circuit 136A, andthe output contact of the inverter INV7 is connected to inverted outputterminal OUTS* of the inverted latch circuit 133A or selection settingcircuit 136A.

In the inverted latch circuit 133A and the selection setting circuit136A which have such a configuration, if the shift clock signal SFC orthe switching control signal SEL is applied, the relevant signal levelis held by the inverters INV4 and INV5. A non-inverted signal and aninverted signal of the present signal levels are each output from thenon-inverted output terminal OUTs and the inverted terminal OUTs* to theshift register circuit 134A as the non-inverted clock signal CK1 andinverted clock signal CK2. Also, the non-inverted signal SLa and theinverted signal SLb are supplied to the write-in current generationcircuit cluster 135A (Each of the write-in current generation circuitsILA1, ILA2, . . . ) and the write-in current generation circuit cluster135B (Each of write-in current generation circuits ILB1, ILB2, . . . ).

<<Drive Control Method>>

Next, the drive control method of the display device which has theconfiguration mentioned above will be explained with reference to thedrawings.

FIG. 27 is a timing chart which shows an example of the drive controloperation in the data driver of this embodiment.

Explanations will also refer accordingly to the configuration of thethird embodiment of the current generation circuit shown in FIG. 6, inaddition to the fourth embodiment of the data driver shown in FIG. 24and FIG. 25.

First, the drive control operation in the data driver 130C, the signalholding operation takes in the display data d0-d3 supplied from thedisplay signal generation circuit 160 to each of the signal latchsections 10 x formed in each current write-in current generation circuitformed by the write-in current generation circuit clusters mentionedabove and is held during a fixed period. The current generation section20 x is formed in the write-in current generation circuit ISx, based onthe holding signals d10-d13 of the display data d0-d3 taken in by thepresent signal holding operation. While performing sequential executionof the current generation supply operation, the write-in current Ipix isgenerated according to the above-mentioned display data d0-d3 andsupplied to each of the display pixels EM via each of the signal linesDL1, DL2, . . . . At the same time as performing this series ofoperations in two sets of write-in current generation circuit clustersfrom the selection setting circuit 136A, while performing theabove-mentioned current generation supply operation from one of thewrite-in current generation circuit cluster, it accomplishes, byperforming repeatedly, an alternate operation to perform simultaneously(in parallel) the above-mentioned signal holding operation from thewrite-in current generation circuit cluster on other side.

Especially, in the data driver related to this embodiment, when and thelike accomplishing a black display operation which performs a lightgeneration operation simultaneously by the minimum luminosity gradationof the pre-display pixels that constitute the display panel, forexample, in addition to the above-mentioned signal holding operation andthe current generation supply operation, while shutting down the supplyof the write-in current Ipix to all of the signal lines DL1, DL2, . . ., it is controlled to apply the specified voltage Vbk (black displayvoltage) to all of the signal lines DL1, DL2, . . . .

First, the signal holding operation, as shown in FIG. 27, after onewrite-in current generation circuit cluster is set into a selectionstate by the selection setting circuit 136A, the signal latch section 10x of this current generation circuit cluster formed in each of thewrite-in current generation circuits ISx based on the shift signals SR1,SR2, . . . outputs sequentially from the shift register circuit 134A.This operation takes in sequentially the display data d0-d3 which shiftsaccording to each line of the display pixels EM (Namely, each of thesignal lines DL1, DL2, . . . ) and performed continuously in one lineperiods. Sequentially from the signal latch section 10 x of the write-incurrent generation circuit ISx where this display data d0-d3 was takenin, the holding signals d10-d13 from a constant period (A period untilone write-in current generation circuit cluster is set into anon-selection state and also the write-in current generation circuitcluster of the other side is set into a selection state by the selectionsetting circuit 136A, based on the following switching control signalSEL.) are output from the signal latch section 10 x to the currentgeneration section 20 x.

Also, as shown in FIG. 27 in the current generation supply operation, inthe “ON/OFF” state a plurality of switch transistors formed in thecurrent generation section 20 x control the composite current of thegradation currents which flow to gradation current transistors connectedto switching transistors that perform an “ON” operation based on theabove-mentioned holding signals d10-d13 sequentially supplied via eachof the signal lines DL1, DL2, . . . as the write-in current Ipix.

Here, the write-in current Ipix is set up so it is suppliedsimultaneously in parallel during a constant period, at least, to eachof the signal lines DL1, DL2, . . . . Also, in this embodiment asmentioned above, a plurality of gradation currents are generated whichhave a current value of a predetermined ratio (For example, 2^(n); n=0,1, 2, 3, . . . ) (see claims 12 and 15 formula) specified from thetransistor size in advance to a single reference current Iref; selectsand integrates the predetermined gradation currents by an “ON/OFF”operation of switch transistors based on the above-mentioned holdingsignal; generates the write-in current Ipix of negative polarity; andflows the write-in current Ipix so it is drawn in the direction of thedata driver 130A from the signal lines DL1, DL2, . . . side.

In the black display operation, as show in FIG. 27, by setting thedisplay data d0-d3 as a black display state (the holding signals d10-d13all zeros (0)), any switch transistor (transistors Tr26-29 shown in FIG.3) formed in the current generation section 20 x that performs an “OFF”operation, the gradation current is interrupted (shut down), and supplyof the write-in current Ipix is suspended. Simultaneously at this time,the black display state (state where the holding signals d10-d13 are setto zero (0)) of the display data is judged from the NOR circuit 31formed in the specified state setting section 30 x, a specified voltageapplication transistor TN32 performs an “ON” operation and the specifiedvoltage Vbk (black display voltage) corresponding to the black display(light generation operation by the minimum luminosity gradation) isapplied sequentially to each of the signal lines DL1, DL2, . . . .

The write-in current generation circuit clusters formed in the datadriver 130A are controlled so two cluster sets alternately set into aselection state. For example, the write-in current Ipix from onewrite-in current generation circuit cluster 135A supplies the displaypixels EM of the oddth lines (odd numbered lines), and the write-incurrent Ipix from the write-in current generation circuit cluster 135Bsupplies the display pixel clusters of the eventh lines (even numberedlines) on the other side.

Consequently, in the data driver 130C and the display device 100Arelated to this embodiment, at the time of an ordinary gradation displayoperation with each of the write-in current generation circuits ISxformed corresponding to each of the signal lines DL1, DL2, . . . ,gradation currents according to the display data d0-d3 are generated,integrated and each of the display pixels EM is supplied with thewrite-in current Ipix which has a suitable current value. While on theother side, at the time of a black display operation, write-in currentIpix from the current generation circuit ISx is interrupted (shutdown).Since the predetermined black display voltage in response to a lightgeneration operation by the minimum luminosity gradation in the displaypixels EM is applied to each of the signal lines DL1, DL2, . . . , it ispossible to attain a favorable gradation display and the specifiedvoltage can successfully stabilize the signal level of each of thesignal lines DL1, DL2, . . . at the time of a black display operation.It can shift to a black display state rapidly and enhancement in thedisplay response characteristics in the display device together with thedisplay image quality can be achieved.

In the write-in current generation circuit ISx in the data driver 130Cwhile applying a current mirror circuit arrangement, by setting thechannel width of a plurality of gradation current transistors whichconstitute the current mirror circuit to the reference currenttransistor, so each one consists of a predetermined ratio (for example,2^(n) gradation), a plurality of gradation currents that have a currentvalue specified with the above-mentioned ratio can be flowed to a singlereference current supplied from a single current generator with thedisplay data d0-d3 (a digital signal which is two or more bits). Sincethe write-in current Ipix has 2^(n) gradation of current value,integrating these suitably is generable. Therefore, a relatively simplecircuit arrangement can generate the write-in current composed of analogcurrent which has a suitable current value corresponding to the displaydata, and a light generation operation of the display pixels EM can beperformed by the proper luminosity gradation.

Also, although the case where the data driver comprising two sets of thewrite-in current generation circuits were applied to each of the signallines arranged to the display panel in this embodiment was explained,this invention is not limited to this and may apply a data driver which,for example, performs the current supply operation and generation of thewrite-in current by taking in and holding the display data seriallycomprising a single write-in current generation circuit to each of thesignal lines.

<<The Fifth Embodiment of the Data Driver>>

Next, the fifth embodiment of the data driver applied to the displaydevice mentioned above will be explained.

Although it has the current sinking method circuit arrangement whichdraws the current in the data driver side from the display pixels EM inthe fourth embodiment of the above-mentioned data driver, the circuitarrangement of the current application method can be applied which flowsin (pours in) the write-in current in the direction of the displaypixels EM from the data driver. The fifth embodiment of the data drivercomprises a circuit arrangement of the current application method.

Furthermore, the data driver of the write-in current generation circuitsconcerning this embodiment resembles the fourth embodiment of the datadriver mentioned above. While two sets are formed in each of the signallines, the write-in current generation circuit of each set withpredetermined operation timing encompasses taking in and holding thedisplay data complementary and continuously, as well as generatingwrite-in current and a configuration that performs a supply operation.When the display data becomes a specified value, it has a configurationwhich supplies specified voltage (black display voltage) to the signallines. Here, in this embodiment, supplied negative reference current hasa constant current value from a single current generator to the write-incurrent generation circuit cluster.

FIG. 28 is a circuit arrangement drawing showing the configuration ofthe fifth embodiment of the data driver in the display device related tothis invention.

FIG. 29 is a circuit arrangement drawing showing one example of thewrite-in current generation circuit applied to the data driver in thisembodiment.

Here, an explanation will be provided matching the configuration of thecurrent generation circuit mentioned above. Furthermore, with referenceto any configuration equivalent in each embodiment mentioned above, thesame or equivalent nomenclature is appended and hereinafter theexplanation is simplified or omitted from the description.

A data driver 130D related to this embodiment, for example, as shown inFIG. 28, is formed with an inverted latch circuit 133B which has aconfiguration equivalent to the fourth embodiment mentioned above and ashift register circuit 134B, whereby the display data d0-d3 in one lineperiods are taken in sequentially to generate the write-in current Ipixaccording to the light generation luminosity in each of the displaypixels EM based on the input timing of the shift signals SR1, SR2, . . .from the shift register circuit 134B; the write-in current generationcircuit clusters 135C and 135D supplied (applicable to poured in/flowedin) via each of the signal lines DL1, DL2, . . . ; and a selectionsetting circuit 136B which operates selectively either of theabove-mentioned write-in current generation circuit clusters 135C and135D based on the switching control signal SEL.

Here, two sets of the write-in current generation circuit clusters 135Cand 135D are formed so, at least, while the display data d0-d3 are inputin common, the reference current Iref which has a constant current valueregulated by the current generator IR may be drawn out in common.

Two sets of the write-in current generation circuit clusters 135C and135D each comprise a plurality of the write-in current generationcircuits ISE1, ISE2, . . . and ISF1, ISF2, . . . . Each of the write-incurrent generation circuits ISE1, ISE2, . . . and ISF1, ISF2, . . . isthe equivalent to the current generation circuit ISB (Hereinaftergenerically named as a write-in current generation circuit ISy) shown inFIG. 8 and is shown in FIG. 29. A signal latch section 10 y isequivalent to the configuration of the fourth embodiment of the currentgeneration circuit. In addition to a current generation section 20 y anda specified state setting section 30 y, an operation setting circuit 40y sets selectively the operating state of each of the write-in currentgeneration circuits ISy based on the switching control signal SEL.

Here, since the signal latch section 10 y, the current generationsection 20 y and specified state setting section 30 y are equivalent tothe signal latch section 10 each shown in FIG. 8, the current generationsection 20B and specified state setting section 30B are omitted fromthis section of the detailed description.

The operation setting 40 y, for example as shown in FIG. 29, has aconfiguration comprising an Pch transistor TP101 which applies aninverted signal of the selection setpoint signal (The non-invertedsignal SLa or the inverted signal SLb) from the selection settingcircuit 136B to the control terminal formed in the current path to thesignal lines DL. An inverter 102 performs a reversal process of theabove-mentioned selection setpoint signal. A NAND circuit 103 performsinput of the shift signal SR from the inverted output of the inverter102 and the shift register circuit 134B as an input. An inverter 104performs the reversal process of the fanout of the NAND circuit 103, andan inverter 105 performs the reversal process further of the invertedoutput from the inverter 104.

In the write-in current generation circuit ILy which has such aconfiguration, if a high-level selection setpoint signal is input fromthe selection setting circuit 134B, a Pch transistor TP101 formed in theoperation setting circuit 40 y will perform an “ON” operation, and thecurrent output contact OUTi of the current generation section 20 y willbe connected to the signal lines DL via the Pch transistor TP101.Concurrently at the same time, a low-level timing control signal isinput to contact CK of the signal latch section 10 y, which isuninvolved with the output of the timing of the shift signal SR, fromthe inverter 102, the NAND circuit 103 and the inverters 104 and 105, aswell as a high-level timing control signal is input regularly to contactCK*. The display data d0-d3 are taken in and the write-in current Ipixaccording to the display data d0-d3 is generated by the currentgeneration section 20 y.

When the display data d0-d3 are all set to zero (0), while the output ofthe write-in current Ipix in the current generation section 20 y isinterrupted (shut down), a specified voltage Vbk (black display voltage)in response to a black display operation is applied to the currentoutput contact OUTi of the current generation section 20 y by thespecified state setting section 30 y so a light generation operation(for example, black display operation) of the display pixel may beperformed in the specified state.

Accordingly, in an ordinary gradation display operation, except a blackdisplay state, a predetermined black specified voltage Vbk (blackdisplay voltage) is applied to the signal lines DL, the write-in currentIpix generated based on the display data d0-d3 is supplied to thedisplay pixels EM via the signal lines DL, thereby interrupting thesupply of the above-mentioned write-in current Ipix in a black displayoperation (The selection state of a write-in current generationcircuit).

On the other side, if a low-level selection setpoint signal is inputfrom the selection setting circuit 134B, the Pch transistor TP101 willperform an “OFF” operation, and the current output contact OUTi of thecurrent generation section 20 y will be separated from the signal linesDL. Also, at this time, a timing control signal which has acomplementary signal level is input to the input contact CK and inputcontact CK* of the signal latch section 10 y in response to the outputtiming of the shift signal SR by the inverter 102 and NAND circuit 103,and inverters 104 and 105. A generation operation of the write-incurrent Ipix is performed by taking in and holding the display datad0-d3.

Accordingly, comparable to the fourth embodiment mentioned above,although the write-in current Ipix is generated based on the displaydata d0-d3, it will be in the state where signal lines DL are notsupplied, and the write-in current generation circuit will beessentially set into a non-selection state.

The drive control operation such as the data driver 130D is same as thatof the fourth embodiment mentioned above, and set in signal holdingoperation. With the signal latch circuits 10 y formed in each write-incurrent generation circuits ISy of the write-in current generationcircuit clusters set as a selection state, based on the shift signalsSR1, SR2, . . . output sequentially from the shift register circuit134B, the display data d0-d3 of each line are taken in sequentially andholding signals d10-d13 equivalent to the inversion signal of thedisplay data d0-d3 are output to the current generation section 20 y.

Additionally, the current generation supply operation selects andintegrates predetermined gradation currents from a plurality ofgradation currents which have a current value specified in advance basedon the holding signals d10*-d13*. Here, the write-in current Ipix ofpositive polarity is generated so the relevant current is supplied(applicable to poured in/flowed in) sequentially in the direction of thedisplay pixels EM via each of the signal lines DL1, DL2, . . . from thedata driver 130B side.

In a black display operation, by setting the display data d0-d3, . . .as a black display state (the holding signals d10-d13 are all set tozero (0)), while generation of gradation currents in the currentgeneration section 20 y and the write-in current Ipix supply aresuspended. A black display state is judged in the specified statesetting section 30 y and the specified voltage Vbk (black displayvoltage) corresponding to the black display (light generation operationby the minimum luminosity gradation) is applied sequentially to each ofthe signal lines DL1, DL2, . . . .

Therefore, also set to the display device which applied the data driver130D related to this embodiment, by generating and integrating thegradation currents according to the display data d0-d3 from each of thewrite-in current generation circuits ISy formed corresponding to each ofthe signal lines DL1, DL2, . . . , each of the display pixels EM can besupplied as the write-in current Ipix which has a suitable currentvalue, and a favorable gradation display operation can be achieved. Onthe other side, at the same time of a black display operation, whileshutting down the write-in current Ipix from each of the currentgeneration circuits ISy, by applying predetermined black display voltageto each of the signal lines DL1, DL2, . . . , it can shift to a blackdisplay state rapidly and enhancement in the display responsecharacteristics in the display device, together with the display imagequality can be achieved.

<<The Sixth Embodiment of the Data Driver>>

Next, the sixth embodiment of the data driver applied to the displaydevice mentioned above will be explained.

While the write-in generation circuits are formed for every signal line;take in, hold and generate the write-in current; and a configurationthat performs a supply operation to predetermined timing, each of thewrite-in current generation circuits are a system comprising the sameconfiguration and write-in current generation circuits as the datadriver of the fifth embodiment. Particularly, it has a specified statesetting section and has a configuration which can accordingly supplyspecified voltage (reset voltage) to the signal lines as a specifiedvalue for the display data. Here, in this embodiment, a negativereference current which supplies a constant value from a single currentgenerator to the write-in current generation circuit clusters.

FIG. 30 is a circuit arrangement drawing showing the configuration ofthe sixth embodiment of the data driver in the display device related tothis invention.

Here, concerning any configuration equivalent in the embodimentsmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

The data driver 130E in this embodiment, for example as shown in FIG. 30has a configuration comprising a shift register circuit 131C, an ORcircuit group 300A, the write-in current generation circuit cluster 137Aand the constant current generator IR. The shift register circuit 131Coutputs shift signals SR1, SR2, SR3 . . . at predetermined timing whileshifting the shift start signal STR based on the shift clock signal SFCsupplied as the data control signal from the system controller 150. TheOR circuit group 300A consists of the OR circuits 301, 302, 303, . . .which output the timing control signal CLK to the write-in currentgeneration clusters 137A mentioned later as the OR operation result thatsets the input signal as the reset control signal RST supplied as thedata control signal from each of the shift signals SR1, SR2, SR3, . . .(Equivalent to the timing control signal CLK mentioned above.) and thesystem controller 150 from the shift register 131C. The write-in currentgeneration circuit clusters 137A consist of a plurality of the write-incurrent generation circuits PXA1, PXA2, PXA3, . . . (Equivalent to thecurrent drive circuit ISA in the third embodiment of the currentgeneration circuit. Hereinafter, described as the write-in currentgeneration circuit PXA for convenience.) which take in sequentially thedisplay data d0-dk (Here, equivalent to the digital signals d0-d3mentioned above which are set to k=3 for convenience of explanation.) inone line periods supplied sequentially from the system controller 150based on the timing control signal CLK output from each of the ORcircuits 301, 302, 303, . . . , generate the write-in current Ipixaccording to the luminescent brightness in each of the display pixels EMin the display panel 110B, and supply to each of the signal lines DL1,DL2, DL3, . . . . The constant current generator IR regularly suppliesthe reference current Iref which has a constant current value via thecommon reference current supply line Ls to each of the write-in currentgeneration circuits PXA1, PXA2, PXA3, . . . formed externally of thedata driver 130E.

Here, the write-in current generation circuits PXA1, PXA2, and PXA3, . .. are comprised of a configuration equivalent to the write-in currentgeneration circuit ISy in the fifth embodiment of the data driver asshown in FIG. 29, which has the signal latch section, the currentgeneration section and the specified state setting section.

<<Pixel Driver Circuit>>

Subsequently, the pixel driver circuit applied to each of the displaypixels EM of the display panel 110B in the display device concerningthis embodiment is explained briefly.

FIG. 31 is a circuit arrangement drawing applicable to the displaydevice in this embodiment showing another example of the configurationof the pixel driver circuit corresponding to the current applicationmethod.

In addition, the pixel driver circuit shown here is only one exampleapplicable to the display device related to this embodiment. Needless tosay, there can be other circuit arrangements which have an equivalentfunction.

As shown in FIG. 31, the pixel driver circuits DCx as applied to thisexample configuration comprises a Pch transistor Tr91, a Pch transistorTr92, a Pch transistor Tr93, an Nch transistor Tr94, and a capacitor Cx.The Pch transistor Tr91 is respectively connected with the drainterminal to the supply Vdd contact, the source terminal to contact Nxa,and the gate terminal to the scanning lines SLa near the intersectingpoint of the scanning lines SLa-SLb and the signal lines DL. The Pchtransistor Tr92 is respectively connected with the drain terminal to thesignal lines DL and the source terminal to contact Nxa, and the gateterminal to the scanning lines Slb. The Pch transistor Tr93 isrespectively connected with the drain terminal to contact Nxa and thesource terminal to contact Nxc, and the gate terminal to contact Nxb.The Nch transistor Tr94 is respectively connected with the drainterminal to contact Nxb and the source to Nxa, and the gate terminal tothe scanning line SLa. The capacitor Cx (retention volume; chargestorage means) is connected in between the contact Nxa and contact Nxb.Here, the supply contact Vdd is connected to a high voltage potentialsupply via the supply line, which is omitted from the diagram, andconstant high potential voltage is applied to predetermined timing.

Furthermore, each of the organic EL devices OEL with which luminescentbrightness is controlled by the luminescent drive current from the pixeldriver circuits DCx, are connected respectively with the anode terminalconnected to the contact Nxc of the above-mentioned pixel drivercircuits DCx and the cathode terminal connected to the low supplyvoltage Vgnd (for example, voltage to ground). Here, the capacitor Cxmay be parasitic capacitance formed in between the gate-source of theNch transistor Tr93, and a capacitative element (a capacitor) can beattached (added) separately in between the gate-source in addition tothe parasitic capacitance.

The drive control operation of the organic EL devices OEL in the pixeldriver circuits DCx which has such a configuration, first, in a write-inoperation period applies a low-level scanning signal Vsel* to thescanning lines SLb as it applies a high-level (selection level) scanningsignal Vsel to the scanning lines SLa. Subsequently, synchronizing withthis timing, the pixel driver circuits DCx supplies the write-in currentIpix to the signal lines DL for performing luminescent operation of theorganic EL devices OEL by predetermined brightness gradation. Here, thewrite-in current Ipix current of positive polarity is supplied and setup so the proper current flows in (pours in) the direction of thedisplay pixels EM (pixel driver circuits DCx) via the signal lines DLfrom the data driver 130E side.

Accordingly, as the transistors Tr92 and Tr94, which constitute thepixel driver circuits DCx perform an “ON” operation, the transistor Tr91performs an “OFF” operation and positive potential corresponding to thewrite-in current Ipix supplied to the signal lines DL is applied tocontact Nxa. Furthermore, as contact Nxb and contact Nxc instantlyconnect with each other, the voltage potential between the gate-sourceof the transistor Tr93 is controlled to the equivalent voltagepotential. Therefore, as transistor Tr93 performs an “OFF” operation,between the ends of capacitor Cx (between contact Nxa and contact Nxb),the voltage potential difference according to the amount of increase inthe write-in current Ipix occurs, and the corresponding electric chargein relation to the voltage potential difference is accumulated and heldas the voltage component.

Subsequently, in the luminescent operation period, as the low-level(non-selection level) scanning signal Vsel is applied to the scanninglines SLa together with a high-level scanning signal Vsel* also appliedto the scanning lines SLb, in synchronizing with this timing, the supplyof the write-in current Ipix is interrupted (shut down). Accordingly,capacitor Cx holds the charge stored up in the write-in operationmentioned above by transistors Tr92 and Tr94 which performed an “OFF”operation and electrically interrupt between the signal lines DL andcontact Nxa, as well as between contact Nxb and contact Nxc.

Thus, when capacitor Cx retains (stores) the charge voltage at the timeof the write-in operation, the voltage potential difference betweencontact Nxa and contact Nxb (between the gate-source of Tr93 of atransistor) will be held, and the transistor Tr93 performs an “ON”operation.

Additionally, by application of the above-mentioned scanning signal Vsel(low-level), transistor Tr91 performs an “ON” operation simultaneously.The luminescent drive current according to the write-in current Ipix(the charge retained in capacitor Cx) flows into the organic EL devicesOEL via transistors Tr91 and Tr93 from the supply contact Vdd (highsupply voltage), and the organic EL devices OEL emit light bypredetermined brightness gradation. Thus, in the pixel driver circuitsDCx as applied to this embodiment, the transistor Tr93 has the functionas the transistor for the luminescent drive.

<<Drive Control Method>>

Next, the operation of the display device which has the configurationmentioned above is explained with reference to the drawings.

FIG. 32 is a timing chart which shows an example of the drive controloperation in the data driver of this embodiment.

FIG. 33 is a timing chart which shows an example of the drive controloperation of the display panel in this embodiment.

Here, in addition to the configuration shown in FIG. 30, explanationwill accordingly refer to the configuration of the current generationcircuit shown in FIG. 4 and FIG. 5.

The drive control operation in the data driver 130E, performs by settingup sequentially a reset operation, a signal holding operation and acurrent generation supply operation. Initially, the reset operationapplies the specified voltage Vr (reset voltage) to each of the signallines DL1, DL2, DL3, . . . via the specified state setting sectionformed in each of the gradation current generation circuits PXA1, PXA2,and PXA3, . . . mentioned above in advance of the signal holdingoperation described later. The signal holding operation outputs during afixed period an inverted signal based on the display data d0-d3 whiletaking in and holding the display data d0-d3 supplied from the displaysignal generation circuit 160 to the data latch sections formed in eachof the gradation current generation circuits PXA1, PXA2, and PXA3, . . .. The current generation supply operation supplies individually each ofthe display pixels EM via each of the signal lines DL1, DL2, DL3, . . .by generating the write-in current Ipix according to the above-mentioneddisplay data d0-d3 from the current generation section formed in each ofthe gradation current generation circuits PXA1, PXA2, and PXA3, . . .based on the output signal from the data latch sections.

Also, the above-mentioned reset operations are performed simultaneouslyto each of the gradation current generation circuits PXA1, PXA2, andPXA3, . . . during periods other than a period that performs the signalholding operation within one horizontal select period and the currentgeneration supply operation, for example, within retrace line periods.Conversely, the signal holding operation and the current generationsupply operation are performed sequentially in each of the gradationcurrent generation circuits PXA1, PXA2, and PXA3, . . . in a periodexcept retrace line periods of one horizontal select period.

Here, as shown in FIG. 32, in a reset operation by supplying ahigh-level reset control signal RST from the system controller 150during the retrace line period before a signal holding operation, ahigh-level timing control signal CLK is output to the data latch sectionprovided in each of the gradation current generation circuits PXA1,PXA2, PXA3, . . . from each of the OR circuits 301, 302, 303, . . . .Further synchronizing with this timing, by supplying display data d0-d3corresponding to a luminescent operation (Equivalent to a black displayoperation) by the lowest brightness gradation from the display signalgeneration circuit 160 as reset data, the taking in and holding of theproper display data d0-d3 (Namely, all zeros (0)) is performedsimultaneously in each of data latch section.

Subsequently, in furnishing a low-level reset control signal RST byoutputting a low level timing control signal CLK to the data latchsection of each of the gradation current generation circuits PXA1, PXA2,PXA3, . . . from each of the OR circuits 301, 302, 303, . . . , anon-inverted output signal of the display-data d0-d3 which were storedas mentioned above is output to the specified state setting section, andthe specified voltage Vr (reset voltage) is applied to each of thesignal lines DL1, DL2, DL3, . . . . Accordingly, the wiring capacityamong other things of each of the signal lines DL1, DL2, DL3, . . . ,the electrical charge stored up in the capacity component, such as theretention volume (capacitor Cx) and the like provided in the displaypixels EM connected to each of the signal lines DL1, DL2, DL3, . . .discharges and each potential is set as a predetermined low potentialstate.

Furthermore, in a signal holding operation, as shown in FIG. 32, bysupplying the low-level reset control signal RST from the systemcontroller 150, the timing control signal CLK responsive to the signallevel of the shift signals SR1, SR2, SR3, . . . that output sequentiallyfrom the shift register circuit 131C are output to the data latchsection of each of the gradation current generation circuits PXA1, PXA2,PXA3, . . . . The operation which takes in sequentially the display datad0-d3 which changes corresponding to each line of the display pixels EM(Namely, each of the signal lines DL1, DL2, DL3, . . . ) from each ofthe data latch sections with timing from the timing control signal CLKbecomes a high-level and is continuously performed in one line periods.Also the state, where the inverted output signal of the display datad0-d3 taken in by the data latch section and outputted to each of thecurrent generation sections, is held during a fixed period (For example,the period until the following high-level signals SR1, SR2, SR3, . . .are outputted.).

Additionally, in the current generation supply operation, the “ON/OFF”state of a plurality of switch transistors (switch transistors Tr26-Tr29shown in FIG. 3) provided in each of the current generation sections arecontrolled based on the inverted output signal outputted from theabove-mentioned data latch sections. The composite current of thegradation currents which flow into the gradation current transistors(transistors Tr22-Tr25 shown in FIG. 3) connected to the switchtransistors which perform an “ON” operation are sequentially suppliedvia each of the signal lines DL1, DL2, DL3, . . . as write-in currentIpix.

Here, the write-in current Ipix, for example, according to all of thesignal lines DL1, DL2, DL3, . . . is set up so it can be supplied inparallel at least during a fixed period. Additionally, in thisembodiment as mentioned above, a plurality of gradation currents, whichhave a current value of a predetermined ratio (For example, 2^(n); n=0,1, 2, 3, . . . ) specified by transistor size relative in advance to thereference current Iref, are generated. When a switch transistor performsan “ON/OFF” operation based on the above-mentioned inverted outputsignal, predetermined gradation currents are selected and integrated;the write-in current Ipix of positive polarity is generated; and thepresent write-in current Ipix is supplied so it will flow (pour) in thedirection of the signal lines DL1, DL2, DL3, . . . from the data driver130E side.

In this embodiment as applied to the data driver 130E, as shown in FIG.30, in contrast the common reference current supply Ls by whichreference current Iref is supplied has a fixed value from the currentgenerator IR and a plurality of gradation current generation circuitsPXA1, PXA2, PXA3, . . . have a configuration connected in parallel.Since the write-in current Ipix is supplied to each of the signal linesDL1, DL2, DL3, . . . (display pixels EM) simultaneously in parallelbased on the display data d0-d3 in each of the gradation currentgeneration circuits PXA1, PXA2, PXA3, . . . , the current supplied toeach of the gradation current circuits PXA1, PXA2, PXA3, . . . via thereference current supply line Ls is not the reference current Irefitself supplied by the current generator IR, but corresponding to thecurrent of a number of gradation current generation circuits (Namely,equivalent to the number of signal lines arranged in the display panel110B, for example, m lines). Thus, the current which has a current value(Iref/m) equally divided will be supplied.

Therefore, the circuit configuration can be set up by m times the ratio,which takes into consideration the above-mentioned current value(Iref/m) supplied to each of the gradation current generation circuitsPXA1, PXA2, PXA3, . . . . This current value ratio (Ratio of the channelwidth of the gradation current transistor to the reference currenttransistor) of each of the gradation currents to reference current isset up in the current mirror circuit section which forms the currentgeneration section of each of the gradation current generation circuitsPXA1, PXA2, PXA3, . . . .

Additionally, as in the other configurations set in each gradationcurrent generation section, a switching means is provided which performsan “ON” operation selectively based on the shift signals SR1, SR2, SR3,. . . output from the shift register circuit 131C, for example, each ofthe gradation current generation circuits PXA1, PXA2, PXA3, . . . . Asthe write-in current Ipix is generated only in the period of the currentgeneration supply operation based on the display data d0-d3, thereference current Iref from the above-mentioned current generator IRremains unchanged and supplies selectively each gradation currentgeneration circuit PXA1, PXA2, PXA3, . . . .

The drive control operation in the display panel 110B is illustrated inFIG. 33, a one cycle scanning period Tsc displays the desired imageinformation on one screen of the display panel 110B representing onecycle. Within the one cycle scanning period Tsc, the display pixels EMconnected to the specified scanning lines are selected. A write-inoperation period Tse (selection period) writes the write-in current Ipixcorresponding to the display data d0-d3 supplied from the data driver130A and is stored as the signal voltage. Based on the stored signalvoltage, the luminescent drive current is supplied to the organic ELdevices OEL according to the above-mentioned display data. A lightgeneration operation period Tnse (non-selection period of the displaypixels EM) which performs luminescent operation by predeterminedbrightness gradation (Tsc=Tse+Tnse) is set up, and drive controlequivalent to the pixel drive circuit DCx mentioned above is performedin each period of operation. Here, the write-in operation period Tse isset for every line so a time overlap does not occur with one another.Also, the write-in operation period Tse is at least set as a periodcomprising a fixed period which supplies in parallel the write-incurrent Ipix to each signal line in the current generation supplyoperation of the above-mentioned data driver 130A.

Specifically, in the write-in operation period Tse to the display pixelsEM, as shown in FIG. 33, by scanning lines SLa and SLb to apredetermined signal level from the scanning driver 120B to the displaypixels EM of a specified line (i-th line), the operation which storessimultaneously the write-in current Ipix supplied in parallel to each ofthe signal lines DL from the data driver 130A as the voltage componentis performed. In the subsequent light operation period Tnse, theoperation to emit light by the brightness gradation corresponding to thedisplay data is maintained by supplying continuously the luminescentdrive current based on the voltage component stored during theabove-mentioned write-in operation to the organic EL devices OEL.

As shown in FIG. 33, by performing repeatedly in sequence such as seriesof drive control operations on each and every line of the display pixelclusters that constitute the display panel 110B, the display data forone screen is written in, each of the display pixels EM emit light bypredetermined brightness gradation and the desired image information isdisplayed.

Therefore, according to the data driver and display device related tothis embodiment, the write-in current Ipix is supplied to the displaypixels EM cluster of a specified line via each of the signal lines DLfrom each of the gradation current generation circuits PXA1, PXA2, PXA3,. . . . In particular, the write-in current Ipix generated consists ofthe constant reference current Iref which is supplied with a signallevel that does not fluctuate and based on the display data d0-d3 of aplurality of digital signal bits from the current generator IR (via thecommon reference current supply line Ls). During the supply time(selection time) of the write-in current Ipix to the display pixels EM,even in the case where the light generation operation is set up brieflyusing relatively low luminosity gradation (When the current value of thewrite-in current Ipix is negligible.) with the high definition displaypanel and the like, the influence of transfer lag (transmission delay)in the signals supplied to the data driver (Each of the gradationcurrent generation circuits PXA1, PXA2, PXA3, . . . ) to generate thewrite-in current Ipix can be eliminated, reduction of the operatingspeed of the data driver can be controlled and enhancement in thedisplay response characteristics in the display device together withdisplay image quality can be achieved.

Also, specifically in the case of the supply operation of the write-incurrent Ipix to each of the display pixels EM, in advance of the signalholding operation and the current generation supply operation in thedata driver 130E, a reset voltage consisting of a constant low voltageis applied to each of the signal lines DL. Because the data driver candischarge sufficiently the electric charge accumulated in thecapacitative wiring (parasitic capacitance) attached to the signal linesand the capacitative element retention volume (capacitor Cx of the pixeldriver circuits) and the like of the display pixels EM, the displaydevice can be initialized (reset). When a selection period of thedisplay pixels EM is set up briefly as the gradation currents arewritten in based on fresh display data, especially when performing alight generation with low luminosity gradation immediately afterperforming a light generation operation with especially high luminositygradation, the influence by the electric charge which remains in theabove-mentioned capacitative element can be eliminated, and the timerequired to stabilize the signal level can be shortened. Therefore,because the level according to the display data can be stabilizedquickly, the signal level applied to the signal lines or the displaypixels and the writing speed to the display pixels can be raised. Also,the display response characteristics and display image quality of thedisplay device can be enhanced.

<<The Seventh Embodiment of the Data Driver>>

Next, the seventh embodiment of the data driver applied to the displaydevice mentioned above will be explained.

Although the above-mentioned data driver in the sixth embodimentcomprises a circuit arrangement corresponding to the current sinkingmethod drawing current write-in current in the direction of the datadriver from the display pixels, this invention is not limited to this.It may be equipped with a circuit arrangement of the current applicationmethod supplied so the write-in current will flow (pour) in thedirection of the display pixels from the data driver.

The data driver concerning this embodiment is configured with a circuitarrangement of the current application method.

FIG. 34 is a circuit arrangement drawing showing a configuration of theseventh embodiment of the data driver in the display device related tothis invention.

Here, concerning any configuration equivalent in the embodimentsmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

As shown in FIG. 34, the data driver 130G related to this embodiment,briefly, has a configuration comprising a shift register circuit 131D,an OR circuit group 300B, the write-in current generation circuitcluster 137B and the current generator IR. The shift register circuit131D which has a configuration equivalent to the data driver 130E shownin FIG. 30; the OR circuit 300B consists of a current supply line Lsconnected to the current generator IR, the OR circuits 301, 302, 303, .. . and a voltage line by which the specified voltage Vr (reset voltage)is applied; and a write-in current generation circuit cluster 137Bconsisting of the write-in current generation circuits PXB1, PXB2, PXB3,. . . (Hereinafter referred to as the write-in current generationcircuit PXB for convenience.) to generate the write-in current Ipixcurrent polarity set up so it will flow (pour) in the direction of thedata driver 130B via each of the signal lines DL from the display panel110D side.

Here, each of the write-in current generation circuits PXB1, PXB2, PXB3,. . . have a configuration comprises a configuration equivalent to thewrite-in current generation circuit ISx in the fourth embodiment of thedata driver shown in FIG. 25 comprising a signal latch section, acurrent generation section, and a specified state setting section.

<<Pixel Driver Circuits>>

Subsequently, the configuration of the pixel driver circuits applied toeach of the display pixels of the display panel 110D related to thisembodiment will be explained.

FIG. 35 is a circuit arrangement drawing applicable to the displaydevice in this embodiment showing another example of the configurationof the pixel driver circuit corresponding to the current sinking method.

The pixel driver circuits shown here only represents an exampleapplicable to the display device related to this invention. Needless tosay, there can be other circuit arrangements having an equivalentoperational function.

As shown in FIG. 35, the pixel driver circuits DCy related to thisembodiment, for example, comprises an Nch transistor Tr101, an Nchtransistor Tr102, an Nch transistor Tr103 and a capacitor Cy. The Nchtransistor Tr101 is individually connected by means of the drainterminal connected to contact Nya, the source terminal connected to thevoltage lines VL arranged in parallel with the scanning lines SL and thegate terminal connected to the scanning lines SL near the intersectingpoint of the scanning lines SL and the signal lines DL. The Nchtransistor Tr102 by means of the source terminal and the drain terminalindividually connected to the signal lines DL and contact Nyb, and thegate terminal connected to the scanning lines SL. The Nch transistorTr103 by means of the source terminal and drain terminal individuallyconnected to the voltage lines VL and contact Nyb, and the gate terminalconnected to contact Nya. The capacitor Cy is connected in betweencontact Nya and contact Nyb.

Additionally, the organic EL devices OEL for light generation luminosityare controlled by the light generation drive current supplied from thepixel driver circuits DCy. The organic EL device OEL anode terminal isconnected to contact Nyb of the above-mentioned pixel driver circuitsDCy, and the cathode terminal is individually connected to the lowsupply voltage Vgnd (voltage to ground). Here, the capacitor Cx may beparasitic capacitance formed in between the gate-source of the Nchtransistor Tr103, and a capacitative element (a capacitor) can beattached separately in between the gate-source in addition to theparasitic capacitance.

Here, as shown in FIG. 34, the voltage lines VL are arranged in parallelto the scanning lines SL and connect in common corresponding to thedisplay pixels EM of each line with one end connected to the voltagedriver 140.

<<Drive Control Method>>

In the drive control operation in the data driver 130B which has such aconfiguration is the same as that of the drive control method (ReferenceFIG. 32) in the sixth embodiment of the data driver mentioned above.Initially, in the reset operation prior to the signal holding operationand the current generation supply operation, by applying a reset controlsignal the specified voltage Vr (reset voltage) is appliedsimultaneously to each of the signal lines DL1, DL2, DL3, . . . by thespecified state setting section formed in each of the write-in currentgeneration circuits PXB1, PXB2, PXB3, . . . setting a predetermined lowpotential voltage state.

Subsequently, in the signal holding operation, a non-inverted outputsignal of the display data d0-d3 taken in sequentially by each line(display pixels EM) from the data latch section of each of the write-incurrent generation circuits PXB1, PXB2, PXB3, . . . is output to each ofthe current generation sections based on the shift signals SR1, SR2,SR3, . . . output sequentially from the shift register circuit 131D.

Also, in the current generation supply operation, based on theabove-mentioned non-inverted output signal from the current generationsections, a plurality of gradation currents are selectively integratedto generate the write-in current Ipix of negative polarity via each ofthe signal lines DL1, DL2, DL3, . . . from each of the display pixels EMside and supplied sequentially so the write-in current Ipix may be drawnin the data driver 130F direction.

In the write-in operation period, the drive control operation of theorganic EL devices OEL in the pixel driver circuits DCy which has such aconfiguration, initially applies the power supply voltage Vsc of alow-level to the voltage lines VL while applying the scanning signalsVsel of a selection level (high-level) to the scanning lines SL. Also,synchronizing with this timing, the write-in current Ipix is supplied tothe signal lines DL from the data driver 130F. Here, as a write-incurrent Ipix supplying current of negative polarity is set up so theproper current will be drawn in the direction of the data driver 130Bvia the signal lines DL from the display pixels EM (pixel drivercircuits DCy) side. Accordingly, while the Nch transistors Tr101 andTr102 which constitute the pixel driver circuits DCy perform an “ON”operation and a low-level of the power supply voltage Vsc is applied tocontact Nya, a low supply voltage level is applied to contact Nyb ratherthan the low-level of the power supply voltage Vsc via the Nchtransistor Tr102 by a drawing in operation of the write-in current Ipix.

In this way, when a voltage potential difference occurs between contactsNya and Nyb (between the gate-source of the Nch transistor Tr103), theNch transistor Tr103 performs an “ON” operation and currentcorresponding to the write-in current Ipix flows in the direction of thesignal lines DL via the Nch transistor Tr103, contact Nyb and the Nchtransistor Tr102 from the voltage lines VL.

At this time, the capacitor Cy electric charge corresponding to thepotential difference produced in between contacts Nya and Nyb isaccumulated and held as the voltage component (the capacitor charges).Also, at this point, since the supply applied to the anode terminal(contact Nxb) of the organic EL devices OEL becomes lower than thesupply (voltage to ground) of the cathode terminal and reverse-biasvoltage is applied to the organic EL devices OEL, the light generationdrive current does not flow into the organic EL devices OEL and a lightgeneration operation is not performed.

Subsequently, in the light generation operation period, while applying anon-selection level (low-level) of the scanning signal Vsel to thescanning lines SL, a high-level of the power supply voltage Vsc isapplied to the voltage lines VL. Synchronizing with this timing, thedrawing in operation of the write-in current Ipix is suspended.

Since application of a voltage level resulting from drawing in operationof a write-in current Ipix to contact Nyb is interrupted (shut down)while the Nch transistors Tr101 and Tr102 perform an “OFF” operation,application of the power supply voltage Vsc to contact Nya isaccordingly interrupted. The capacitor Cy then holds the electric chargestored in write-in operation mentioned above.

In this way, when the capacitor Cx holds the charge voltage at the timeof the write-in operation, the voltage potential difference betweencontacts Nya and Nyb (between gate-source of the Nch transistor Tr103)will be held, and Nch transistor Tr103 maintains an “ON” state. Also,because the power supply voltage which has a voltage level higher thanthe voltage to ground is applied to the voltage lines VL, the lightgeneration drive current flows into the organic EL devices OEL in theforward-bias direction via Nch transistor Tr103 and contact Nyb from thevoltage lines VL.

Here, because the potential difference (charge voltage) held in thecapacitor Cy is equivalent to the potential difference when the currentflows corresponding to the write-in current Ipix to the Nch transistorTr103 at the time of the above-mentioned write-in operation, the lightgeneration drive current which flows into the organic EL devices OELwill have a current value equal to the above-mentioned current. Theorganic EL devices OEL continue operation to emit light by the desiredluminosity gradation in the light generation operation period, based onthe voltage component corresponding to the gradation currents written inthe write-in operation period.

Further, like the series of drive control operations, shown in FIG. 33using the scanning driver 120A, voltage driver 140 and the data driver130F, by performing them repeatedly in sequence on each and every lineof the display pixel clusters that constitute the display panel 110B,the display data for one screen is written in, each of the displaypixels EM emit light by predetermined brightness gradation and thedesired image information is displayed.

Therefore, also established in the display device as applied to the datadriver 130F related to this embodiment, by the reset operation theelectric charge accumulated in the capacitative element attached to thesignal lines DL or the display pixels EM is fully discharged. Afterwardsit initializes in a predetermined low supply state and each of thegradation currents supplied to the display panel (display pixels) can begenerated and supplied based on the display data consisting of thereference current of a constant current value and the digital signals.At the same time, it can control any reduction in the data driveroperating speed resulting from the charge and discharge operation of thecapacitative element attached to the signal lines, the reference currentsupply line or the like, as well as enhance the display responsecharacteristics. The gradation currents which have a suitable currentvalue according to the display data from the gradation current supplycircuits individually formed corresponding to each of the signal linescan be generated, each of the display pixels can be supplied, and afavorable gradation display can be achieved.

<<The Eighth Embodiment of the Data Driver>>

Subsequently, the eighth embodiment of the data driver applied to thedisplay device concerning this embodiment will be explained.

The data driver related to this embodiment is the same as the fifthembodiment of the data driver mentioned above is comprised with two setsof the write-in current generation circuits formed in each of the signallines. Each set of the write-in current generation circuits perform takein and holding of the display data, generate write-in current, as wellas a supply operation complementarily and successively according topredetermined operation timing. Each of the write-in current generationcircuits comprises the same configuration as the write-in currentgeneration circuit in the sixth embodiment of the data driver. Specifiedvoltage (reset voltage) can be supplied for the display data to thesignal lines as a specified value. Here, in this embodiment, the datadriver is constituted so that negative reference current which has aconstant value from a single current generator can be supplied to eachof the write-in current generation circuit clusters formed in the twosets.

FIG. 36 is a circuit arrangement drawing showing the configuration ofthe eighth embodiment of the data driver in the display device relatedto this invention.

Here, concerning any configuration equivalent in the embodimentsmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

As shown in FIG. 36, the data driver 130G related to this embodiment hasa configuration comprising the same configuration as the fifthembodiment of the data driver mentioned above. Specifically, the datadriver 130G comprises an inverted latch circuit 133C, a shift registercircuit 134C, the OR circuit group 300C, a selection setting circuit136C and the current generator IR. The inverted latch circuit 133Cgenerates the non-inverted clock signal CKa and the inverted clocksignal CKb based on the shift clock signal SFC supplied from the systemcontroller 150; a shift register circuit 134C outputs sequentially theshift signals SR1, SR2, SR3, . . . to predetermined timing, whileshifting the shift start signal STR based on the non-inverted clocksignal CKa and the inverted clock signal CKb; the OR circuit group 300Cconsists of the OR circuits 301, 302, 303, . . . which output in commonthe OR operation result of the reset control signal RST supplied fromeach of the shift signals SR1, SR2, SR3, . . . (Hereinafter described asthe shift signals SR for convenience hereafter) and the systemcontroller 150 as the timing control signal CLK to the write-in currentgeneration circuit clusters 138C and 138D described later. Two sets ofthe write-in current generation circuit clusters 138C and 138D take insequentially the display data d0-d3 in one line periods which aresupplied sequentially from the display signal generation circuit 160based on the timing control signal CLK output from each of the ORcircuits 301, 302, 303, . . . , generate the write-in current Ipixcorresponding to the light generation luminosity in each of the displaypixels EM and then supplied (applied) via each of the signal lines DL1,DL2, DL3, . . . ; a selection setting circuit 136C generates theselection setpoint signal (The non-inverted signal SLa and the invertedsignal SLb of the switching control signal SEL) for operatingselectively either of the above-mentioned write-in current generationcircuit clusters 138C and 138D based on the switching control signal SELsupplied as the data control signal from the system controller 150; andthe current generator IR (current of negative polarity is supplied anddrawn out) supplies constant reference current Iref via each of thewrite-in current generation circuits PXC1, PXC2, PXC3, . . . and PXD1,PXD2, PXD3, . . . (Hereinafter referred to as the write-in currentgeneration circuits PXC and PXD for convenience.) which constitute thewrite-in current generation circuit clusters 138C and 138D, and a commonreference current supply line Ls.

Here, the inverted latch circuit 133C, the shift register circuit 134Cand the selection setting circuit 136C are each equipped with aconfiguration equal to the inverted latch circuit 133B in the fifthembodiment of the data driver, the shift register circuit 134B and theselection setting circuit 136B.

In addition, each of the write-in current supply circuits PXC and PXDhave a configuration which comprises a configuration equal to thewrite-in current generation circuits ISy in the fifth embodiment of thedata driver shown in FIG. 29 and equipped with the signal latch section10 y, the current generation section 20 y and the specified statesetting section 40 y.

In the write-in current generation circuits PXC and PXD which have sucha configuration, when the selection setpoint signal of a selection levelis input from the selection setting circuit 136C, based on invertedoutput signals d10*-d13* output from the data latch sections 10 y, thewrite-in current Ipix according to the display data d0-d3 is generatedin the current generation section 20 y. Concurrently, the display pixelsEM are supplied via the signal lines DL and the write-in currentgeneration circuits PXC or PXD are set into a selection state.

Conversely, when a non-selection level of the selection setpoint signalis input from the selection setting circuit 136C, although the displaydata d0-d3 are taken in and held in the data latch sections 10 y thewrite-in current Ipix is not generated, but the signal lines DL will besupplied and the write-in current generation circuits PXC or PXD will beset into a non-selection state.

Specifically, the selection setting circuit 136C, by settingappropriately the selection setpoint signal (The non-inverted signal SLaor the inverted signal SLb of the switching control signal SEL) input tothe two sets of write-in current generation circuit clusters 138C and138D, either of the two sets of write-in current generation circuitclusters 138C and 138D can be set into a selection state and the otherside can be set into a non-selection state.

<<Drive Control Method>>

Next, the operation of the display device which has the configurationmentioned above will be explained with reference to the drawings.

FIG. 37 is a timing chart which shows an example of the drive controloperation of the data driver in this embodiment.

In the drive control operation in the data driver 130G, first, in twosets of the write-in current generation circuit clusters with one sideset as a non-selection state, the signal holding operation sequentiallytakes in and holds the display data d0-d3 corresponding to each of thedisplay pixels EM in each of the write-in current generation circuits(data latch sections) formed in these write-in current generationcircuit clusters. The reset operation sets the specified state of eachof the write-in current generation circuit clusters via each of thewrite-in current generation circuits (specified state setting section)and applies simultaneously the specified voltage Vr (reset voltage) toeach of the signal lines DL and discharges the stored charge. A currentsupply operation generates the write-in current Ipix corresponding tothe display data d0-d3 held in the above-mentioned signal holdingoperation by each of the write-in current generation circuits (currentgeneration sections) which is supplied sequentially to each of thedisplay pixels EM via each of the signal lines DL to perform thesetting. Further, such a series of setting operations is performedsuccessively and alternately in the two sets of write-in currentgeneration circuit clusters.

The drive control operation in the data driver 130G, as shown in FIG.37, first the switching control signal SEL is supplied from the systemcontroller 150. In the signal holding operation, after one of thewrite-in current generation circuit clusters (For example, write-incurrent generation circuit cluster 138C) is set in a non-selection stateby the selection setting circuit 136C, based on the shift signals SR1,SR2, SR3, . . . output sequentially from the shift register circuit134C, the display data d0-d3 is taken in sequentially which shiftscorresponding to each line of the display pixels EM (Namely, each of thesignal lines DL1, DL2, DL3, . . . ) into each of the write-in currentgeneration circuits PXC1, PXC2, PXC3, . . . that constitute the write-incurrent generation circuit cluster 138C, and the holding operation iscarried out successively in one line periods.

Subsequently, in a reset operation after the selection setting circuit136C sets the selection state by supplying the switching control signalSEL from the system controller 150, the display data d0-d3 correspondingto the specified state (Equivalent to a black display state) are takenin simultaneously through supplying the reset control signal RST in eachof the write-in current generation circuits PXC1, PXC2, PXC3, . . . ofthe write-in current generation circuit cluster 138C. Accordingly, thespecified voltage Vr (reset voltage) is applied simultaneously to eachof the signal lines DL from each of the write-in current generationcircuits PXC1, PXC2, PXC3, . . . , and the electric charge accumulatedin the capacitative element attached to each of the signal lines DL1,DL2, DL3, . . . and the display pixels EM discharges.

Subsequently, in the current generation supply operation based on thedisplay data d0-d3 held in the above-mentioned signal holding operationin each of write-in current generation circuits PXC1, PXC2, PXC3, . . .(data latch sections), by integrating selectively a plurality of thegradation currents which are set so each one has a different currentvalue ratio, the write-in current Ipix which specifies the luminositygradation in each of the display pixels EM is generated and suppliedsequentially via each of the signal lines DL1, DL2, DL3, . . . .

Furthermore, as shown in FIG. 37, such a series of operations isalternately performed repeatedly between the two sets of the write-incurrent generation circuit clusters 138C and 138D. Namely, one of thewrite-in current generation circuit cluster 138C is set as anon-selection period while performing the signal holding operation whichtakes in the display data and the other write-in current generationcircuit 138D is set as a selection period. After carrying out a resetoperation, the gradation currents are generated and supplied based onthe display data taken in with the previous timing and performs aparallel gradation current supply operation. Subsequently, whileperforming the next reset operation, the write-in current generationcircuit cluster 138C is set as a selection period and the currentgeneration supply operation in the other write-in current generationcircuit 138D is set as a non-selection period, while performing thesignal holding operation which takes in the display data. This shiftingback and forth between the write-in current generation circuits iscarried out repeatedly in an alternating sequence.

Therefore, also set to the display device as applied to the data driver130G related to this embodiment, the electric charge accumulated in thecapacitative element attached to the signal lines DL or the displaypixels EM from a reset operation is fully discharged. For that reason itinitializes in the predetermined low supply state and each of thegradation currents supplied to the display panel (display pixels EM) canbe generated and supplied afterwards based on the display dataconstituted by the reference current of a constant current value and thedigital signals. At the same time, it can control any reduction in thedata driver operating speed resulting from the charge and dischargeoperation of the capacitative element attached to the signal lines, thereference current supply line or the like, as well as enhance thedisplay response characteristics. The gradation currents which have asuitable current value according to the display data from the gradationcurrent supply circuits individually formed corresponding to each of thesignal lines can be generated, each of the display pixels EM can besupplied, and a favorable gradation display can be achieved.

Additionally, by having two sets of write-in current generation circuits(clusters), repeating alternately the operation state of each of thewrite-in current generation circuits and performing this operation toeach of the signal lines, and in view of the fact that the gradationcurrents have a current value corresponding appropriately to the displaydata and can be supplied continuously to each of the display pixels fromthe data driver, the light generation operation of the display pixels bypredetermined luminosity gradation can be performed rapidly, as well asthe display response speed and the display image quality can be furtherenhanced.

Moreover, in each embodiment of the data driver mentioned above,although the data driver has such a configuration which supplies incommon the reference current from a single current generator with regardto supplying the reference current in a plurality of write-in currentgeneration circuits formed in the data driver, this invention is notlimited to this. It may have a constant current source for every datadriver. Besides, it may have a constant current source for everygradation current generation circuit of a predetermined number of aplurality of gradation current generation circuits formed within asingle data driver.

Next, as in the sixth through eighth embodiments mentioned above, thecapacitative wiring attached to the signal lines and the like in priorto the operation which writes the gradation currents to the displaypixels (parasitic capacitance) based on the display data or by thedischarging (reset operation) the electric charge which remains in thecapacitative element retention volume of the display pixels and the liketo predetermined low supply voltage, the circuit arrangement of the datadriver was made to realize a composition which shortens the timerequired to stabilize the appropriate signal levels according to thedisplay data in the write-in operation of the gradation currents to thedisplay pixels.

However, this invention is not limited to these configurations and canbe made to achieve the technical concept that performs a reset operationaccording to the configuration of the pixel driver circuits which formseach of the display pixels. Hereinafter, explained in detail.

<<Other Examples of the Configuration of the Pixel Driver Circuits>>

FIG. 38 is a circuit arrangement drawing showing another example of theconfiguration which is the display pixels applicable to the displaydevice concerning this invention.

FIG. 39 is a circuit arrangement drawing showing another example of theconfiguration of the display pixels applicable to the display devicerelated to this invention.

Although applied suitably for the display device concerning thisinvention, the configuration of the display pixels in this embodimentemploys the data driver of the first and fifth embodiments mentionedabove, the data driver side is not limited only to these configurationsand may be equipped with other supplementary configurations.

Additionally, the configuration in FIGS. 38-39 is shown in FIG. 21.Although the reset mechanism is attached based on the above-mentionedtechnical concept by considering the fundamental construction of thepixel driver circuit configuration corresponding to the currentapplication method, the fundamental configuration of the pixel drivercircuits is not limited to this. As long as the circuit has a series ofoperational steps including the write-in operation and the lightgeneration operation mentioned above and comprises light emittingdevices for the light generation operation, other circuit arrangementscan be applied, for example, the pixel driver circuit shown in FIG. 16.

As shown in FIG. 38, the transistor cluster of the pixel driver circuitsDCxa for the display pixels EM related to this example configuration hasthe same circuit arrangement as the pixel driver circuits DCy shown inFIG. 21, which comprises as mentioned above the Pch transistors Tr81 andTr83 and the Nch transistors Tr82 and Tr84, along with the capacitor CY.This example of the pixel driver circuits DCxa further comprises an Nchtransistor Tr85. In addition to the retention volume (capacitor Cx inthis example) and the organic EL device OEL (optical element), the Nchtransistor Tr85 (discharge circuit) is connected by means of the controlterminal (gate terminal) to the reset line RL arranged in parallel withthe scanning lines SL and connected in the current path (source-drainterminals) in between contact Nxc and the low supply voltage Vgnd.

Furthermore, as shown in FIG. 38, although the configuration shownconnects the Nch transistor Tr85 that has a reset function in betweencontact Nxc and the low supply voltage Vgnd, this invention is notlimited to this. As shown in FIG. 39, the pixel driver circuits DCxb maybe configured with the Nch transistor Tr85 connected in between contactNxa and the low supply voltage Vgnd.

Also, in the pixel driver circuits DCxa and DCxb shown in FIGS. 38-39,respectively, though Tr82 consists of an Nch transistor and has acircuit arrangement with the control terminal connected to the scanninglines SL, the operational function in the pixel driver circuits is equalto the operational function of the pixel driver circuit shown in FIG.21.

In such a configuration, by applying a high-level reset control signalRST to the reset line RL from the system controller 150, the Nchtransistor Tr85 performs an “ON” operation by means of connectingelectrically between the ground potential of the pixel driver circuitsDCxa contact Nxc or the pixel driver circuits DCxb contact Nxa. Anelectric charge is accumulated (held) in the retention volume (capacitorCx) of each of the pixel driver circuits DCxa and DCxb, which dischargesto ground potential via the Nch transistor Tr85, and a reset operationof the display pixels EM is performed.

<<Drive Control Method>>

FIG. 40 is a timing chart which shows an example of the drive controloperation in the display device related to this embodiment.

Here, the data driver which has the configuration of the firstembodiment shown in FIG. 17 will be explained.

The drive control operation in the display device related to thisembodiment performs by setting up sequentially, first, a reset operationwhich discharges the electric charge accumulated in the capacitativeelement attached to each of the display pixels EM prior to the supplyoperation of the write-in current from the data driver 130A; a signalholding operation which takes in and holds the display data suppliedfrom the display signal generation circuit 160 to each of the write-incurrent generation circuits ILA1, ILA2, ILA3, . . . of the data driver;and a current generation supply operation which generates the write-incurrent Ipix based on the held display data and is supplied to each ofthe signal lines DL.

The drive control operation in the display device related to thisembodiment, as shown in FIG. 40, initially preceded by the resetoperation, this function generates the write-in current according to thedisplay data from the data driver 130A which is supplied via the signallines DL. A high-level reset control signal RST is provided via thereset line RL from the system controller 150 to the display pixelclusters lines set to a selection state in order for the write-in of theabove-mentioned gradation currents. Simultaneously, Nch transistor Tr85formed in each of the display pixels EM performs an “ON” operation andconnects the specified contacts Nxc and Nxa of the pixel driver circuitsDCxa and DCxb to ground potential. Accordingly, the electric charge isaccumulated as the retention volume in the capacitative element(capacitor Cx) and the like formed in the pixel driver circuits DCxa andDCxb then discharges to ground potential. The potential of each of theabove-mentioned contacts Nxc and Nxa is initialized in a predeterminedlow-level potential state (reset).

Subsequently, in the signal holding operation, the same as each of theembodiments mentioned above, the operation takes in sequentially andholds the display data performed successively in one line periods andplaces the display data in the current generation supply operation. Byselectively integrating a plurality of gradation currents, which areeach set to a current value of a different ratio based on the displaydata held mentioned above, generates the write-in current Ipix which issupplied sequentially to the display pixels EM via each of the signallines DL.

In the succeeding light generation operation, each of the display pixelsEM emits light by the luminosity gradation corresponding to the displaydata by supplying continuously the light generation drive current to theorganic EL devices OEL based on the held voltage component. The write-incurrent Ipix is written in simultaneously and supplied in parallel toeach of the signal lines DL from the data driver 130A and held as thevoltage component in capacitor Cx. By applying the scanning signal of aselection level to the scanning lines SL from the scanning driver 120Ato the display pixel clusters discharges the electric charge accumulatedin the capacitative element from the above-mentioned reset operation.

Accordingly, as the display device applied to the display panel (displaypixels EM) related to this embodiment can be initialized in thepredetermined low potential state, the electric charge accumulated inthe capacitative element attached to the display pixels EM from a resetoperation can be discharged favorably. Furthermore, it is also possibleto set the appropriate amount of electrical charge to be accumulatedaccording to the gradation currents generated based on the display data,as well as set the light generation drive current supplied to theorganic EL devices OEL as a suitable current value. Consequently, at thesame time degradation of the writing speed to the display panelresulting from the charge and discharge operation of the capacitativeelement attached to the display pixels EM can be controlled whileenhancing the display response characteristics. Also, the lightgeneration operation of each of the display pixels EM (organic ELdevices) can be performed by the proper luminosity gradation accordingto the display data, and a favorable gradation display is achievable.

As mentioned above in this embodiment, since this configurationcomprises a reset mechanism (the Nch transistor Tr85 and the reset lineRL) for discharging the stored charge in advance of the write-inoperation of the gradation currents to the display pixels EM (pixeldriver circuits), the reset mechanism (For example, the specified statesetting section formed in each of the write-in current generationcircuits shown in FIG. 30 and the OR-circuit group) in the data drivercan be omitted, the circuit arrangement can be simplified andminiaturization of the display device can be achieved.

In addition, the display device related to each embodiment mentionedabove illustrated only when setting the current polarity so the lightgeneration drive current flows in the direction of the light emittingelements (organic EL devices) from the pixel driver circuits that formsthe display pixels, but this invention is not limited to this. Thisinvention may be constituted so the light generation drive current flowsin the direction of the pixel driver circuits from the light emittingelements by inversely connecting the input/output terminals of the lightemitting devices while connecting the high potential voltage to theother side of the light emitting devices.

<<The Second Embodiment of the Display Device>>

Next, in the current generation circuit related to this invention, anembodiment with regard to applying the pixel driver circuits formed ineach of the display pixels which constitutes the display panel in thedisplay device will be explained with reference to the drawings.

FIG. 41 is an outline block diagram showing an example of oneconfiguration of the second embodiment of the display device related tothis invention.

FIG. 42 is a circuit arrangement drawing showing one embodiment of thepixel driver circuit applied to the display device in this embodiment.

FIG. 43 is a circuit arrangement drawing showing one embodiment of thedata driver applied to the display device in this embodiment.

Here, concerning any configuration equivalent in the embodimentsmentioned above, the same or equivalent nomenclature is appended and theexplanation is simplified or omitted from the description.

As shown in FIG. 41, the display device 100C related to this embodiment,briefly, comprises the same configuration as the first embodiment of thedisplay device shown in FIG. 13. Although this configuration comprisesthe display panel 110E, the scanning driver 120C, the data driver 130H,the system controller 150 (not shown) and the display signal generationcircuit 160 (not shown), the pixel driver circuits DCz in each of thedisplay pixels EP which forms the display panel 110E and thecorresponding data driver 130H has a different configuration as shownbelow.

Specifically, the display panel 110E applied to this embodiment, asshown in FIG. 41, has a configuration comprised of a plurality ofscanning lines SL, two or more sets of signal line groups DLz, aplurality of display pixels EP and a current generator IR. Inparticular, this configuration comprises a plurality of scanning linesSL arranged in parallel; two or more sets of the signal line groups DLz(four in this embodiment) arranged respectively as one set of aplurality to intersect at right angles with the scanning lines SL; aplurality of display pixels EP arranged near the intersecting point ofthe scanning lines SL and signal line groups DLz (In FIG. 41, theconfiguration consists of the pixel driver circuits DCz and the organicEL devices OEL (optical elements) which are described later); and acurrent generator IR regularly supplies the reference current which hasa constant current value in the display pixels EP.

Here, as shown in FIG. 41, the pixel driver circuits DCz configurationscomprise the light generation drive and the organic EL devices OEL(optical elements). The light generation drive generates lightgeneration drive current based on the scanning signals Vsel applied toeach of the display pixels EP via the scanning lines from the scanningdriver 120C and the gradation data DP0-DPk (digital signals; referred toas k=3 in this embodiment) supplied via the signal line groups DLz fromthe data driver 130H; and the organic EL devices OEL (optical elements)perform light generation operation by predetermined luminosity gradationaccording to the current value of the light generation drive currentsupplied by the pixel driver circuits DCz.

<<Pixel Driver Circuits>>

The configuration formed in each embodiment of the current generationcircuit mentioned above is applied to the pixel driver circuits DCz inthis embodiment shown in FIG. 42 which comprises the signal latchsection 10 z (For example, equivalent to the signal latch section 10 inFIG. 1) and the current generation section 20 z (For example, equivalentto the current generation section 20A in FIG. 1). The signal latchsection 10 z takes in individually and simultaneously the output signalscorresponding to the proper gradation data DP0-DP3 containing thegradation data DP0-DP3 in one line periods supplied via each of thesignal line groups DLz from the data driver 130H based on the appliedtiming of the scanning signal Vsel from the scanning driver 120C; andperforms by holding the output of the holding signals d10-d13 for apredetermined period corresponding to the proper gradation data DP0-DP3.The current generation section 20 z integrates the specified gradationcurrents selected from the above-mentioned holding signals d10-d13 amonga plurality of gradation currents generated based on the referencecurrent Iref supplied via the reference current supply line Ls to eachof the display pixels EP; and generates the light generation drivecurrent corresponding to the luminosity gradation in each of the displaypixels EP which is supplied to the organic EL devices OEL (opticalelements). Also, the configuration of this pixel driver circuits DCz isequal to the current generation circuit (Reference FIG. 1) related tothis invention. Here, the current latch section 10 z has a configurationcomprising multiple (four sets) latch circuits corresponding to each ofthe gradation data DP0-DP3, as well as the configuration of the signallatch section 10 shown in FIG. 1. Furthermore, the cathode terminal ofthe organic EL device OEL is connected to the current output contactOUTi of the current generation section 20 z while the anode terminal isconnected to voltage contact +V connected to the predetermined highpotential voltage.

Initially, the drive control operation of the organic EL device OEL inthe pixel driver circuits DCz which has such a configuration, whileapplying a high-level (selection level) scanning signal Vsel to thescanning lines SL, the operation synchronizes with this timing. Thegradation data DP0-DP3 consisting of a plurality of digital signal bitscorresponding to the display data d0-d3 provided from the display signalgeneration circuit 160 by the data driver 130H (described later) is thensupplied to the signal line clusters DLz.

Accordingly, the gradation data DP0-DP3 are taken in individually andsimultaneously for holding at each of the signal input contacts IN0-IN3of the signal latch section 10 z which forms part of the pixel drivercircuits DCz. The holding signals d10-d13 based on each of the gradationdata DP0-DP3 are output to current generation section 20 z.

The current generation section 20 z, for example, which is the same ascurrent generation section 20A in the first embodiment of the currentgeneration circuit mentioned above, supplies the light generation drivewhich is acquired and integrated and then selects only the specifiedgradation currents from a plurality of gradation currents that have acurrent value of a predetermined ratio. The specified gradation currentsare then generated based on reference current Iref according to a signallevel of above-mentioned holding signals d10-d13 to the organic ELdevices OEL via the current output contact OUTi (In this embodiment, thelight generation drive current flows so it is drawn in the direction ofthe pixel driver circuits DCz from the organic EL devices OEL side).

Accordingly, the light generation drive current according to the displaydata d0-d3 (gradation data DP0-DP3) flows in the forward-bias directioninto the organic EL devices OEL, and the organic EL devices OEL emitlight by predetermined luminosity gradation.

<<Data Driver>>

The data driver 130H, for example, the shift register circuit 131E has aconfiguration equivalent to the embodiment mentioned above as shown inFIG. 43. Particularly, this configuration comprises the latch circuits140, the output circuits 141, the system controller 150 (not shown) andthe signal generation circuit 160 (not shown). The latch circuits 140contain a plurality of the latch sections LD1, LD2, LD3, . . . whichtake in individually and sequentially a plurality of display data d0-d3bits supplied from the display signal generation circuit 160 (not shown)and hold them based on the input timing of the shift signals SR1, SR2,SR3, . . . from the shift register circuit 131E; and the output circuits141 contain a plurality of switches SW1, SW2, SW3 which perform theoperation to supply collectively the display data d0-d3 in one lineperiods held in the latch circuits 140 as the gradation data DP0-DP3 viaeach of the signal line clusters DLz to each of the display pixels EPmentioned above based on an output enable signal WE output from a systemcontroller 150 (not shown).

<<Drive Control Method>>

Next, the operation of the display device which has the configurationmentioned above will be explained with reference to the drawings.

FIG. 44 is a timing chart which shows an example of the drive controloperation in the display device in this embodiment.

FIG. 45 is a circuit arrangement drawing showing another embodiment ofthe pixel driver circuit applied to the display device in thisembodiment.

First, the drive control operation in the data driver 130H, as shown inFIG. 44, performs by setting up the display data holding operation whichtakes in sequentially the display data d0-d3 supplied to each of thelatch sections LD1, LD2, LD3, . . . which form the latch circuit 140mentioned above from the display signal generation circuit 160, andholds this display data; and a gradation data supply operation suppliescollectively the display data d0-d3 taken in by the display holdingoperation to each of the signal line groups DLz as gradation dataDP0-DP3 via each of the switches SW1, SW2, SW3, . . . of the outputcircuit 141.

Here, the display data holding operation takes in sequentially thedisplay data d0-d3 which shifts in response to each line of the displaypixels EP in each of the above-mentioned latch sections LD1, LD2, LD3, .. . based on the shift signals SR1, SR2, SR3, . . . output sequentiallyfrom the shift register circuit 131E and the holding operation iscontinuously performed in one line periods.

Furthermore, in the gradation data supply operation, the signal linegroups DLz are supplied collectively via each of the switches SW1, SW2,SW3, . . . by using the display data d0-d3 as the gradation data DP0-DP3held at each of the above-mentioned latch sections LD1, LD2, LD3, . . .based on the output enable signal WE output from the system controller150. Here, the gradation data supply operation in the display panel 110Eis set up to synchronize with the applied timing of the scanning signalVsel which selects the display pixels EP of a specified line. Thus, inthis embodiment, the gradation data DP0-DP3 (digital signals) based onthe display data d0-d3 which consist of a plurality of digital signalbits is supplied to the direct presentation pixels (pixel drivercircuits DCz) via each of the signal line clusters DLz arranged in thedisplay panel 110E from the data driver 130H.

In the drive control operation in the display panel 110E (display pixelsEP), as shown in FIG. 44, by applying the scanning signal Vsel to thescanning lines SL of a specified line (i-th line) from the scanningdriver 120C, the gradation data DP0-DP3 supplied to each of the signalline clusters DLz by the above-mentioned gradation data supply operationfrom the data driver 130H are taken in and held in the signal latchsections 10 z formed in each of the display pixels EP (pixel drivercircuits DCz), and the holding signals DP10-DP13 based on the gradationdata DP0-DP3 are output to the current generation section 20 z.

Moreover, as mentioned above, based on the reference current Iref andthe holding signals DP10-DP13, the current generation section 20 zgenerates the light generation drive current according to the displaydata d0-d3 (gradation data DP0-DP3) and supplies the current to theorganic EL devices OEL. Accordingly, the organic EL devices OEL emitlight by predetermined luminosity gradation.

Also, the display panel 110E (pixel driver circuits DCz) related to thisembodiment, as shown in FIG. 41, is set to the same circumstances shownin each embodiment that has a configuration whereby a plurality ofdisplay pixels EP (pixel driver circuits DCz) are connected to a commonreference current supply line Ls supplied by reference current Iref fromthe current generator IR as shown in FIG. 44. Since the light generationdrive current to each of the organic EL devices OEL is generatedsimultaneously based on the gradation data DP0-DP3 in each of the pixeldriver circuits DCz synchronizing with timing applied by the scanningsignal Vsel that selects the display pixels EP of a specified line, thecurrent supplied to the display pixels EP (pixel driver circuits DCz) ofeach line via the reference current supply line Ls is not the referencecurrent Iref itself supplied from the current generator IR. This currentwill have a current value (Iref/m) by which almost equal division wasperformed and supplied according to the number (For example, m lines) ofthe display pixels EP (pixel driver circuits DCz) of each line.

Sequential execution of a series of the above drive control operationsis performed on each and every line that forms the display panel 110E.Furthermore, the light generation operation (supply operation of thelight generation drive current) of the organic EL devices OEL of eachline is continuously held by the pixel driver circuits DCz until thenext scanning signal Vsel is applied.

Therefore, set to the display device 100C related to this embodiment,via each of the signal line groups DLz arranged in the display panel110E from the data driver 130H, the gradation data DP0-DP3 consisting ofa plurality of digital signal bits corresponding to the display datad0-d3 are directly supplied directly to the display pixels EP (pixeldriver circuits), and set to the pixel driver circuits. Because thelight generation drive current consists of an analog signal generatedbased on the reference current Iref supplied via a common referencecurrent supply line Ls from a current generator IR (current composed ofreference current Iref that is equally divided by the relevant number ofwrite-in current generation circuits), as compared with a configurationwhich supplies write-in current that constitutes the display pixels EPfrom analog current and used abundantly in conventional technology, aswell as the effects of signal level degradation, external noise and thelike all can be markedly improved upon to offset these negativeinfluences. As a direct result of this invention, the signal-to-noise(S/N) ratio can be improved, the light generation operation of theorganic EL devices (light emitting elements) can also be accomplished bythe appropriate luminosity gradation corresponding to the display data,and enhancement in the display image quality can be achieved as well.

In addition to the embodiment and circumstances which were mentionedabove, regarding the signal lines relevant to the light generationoperation in the display pixels, because it does not have aconfiguration which flows an analog signal that changes signal levels,this alleviates the limitation on the operating speed resulting from thecharge and discharge operation of the signal lines, as well as enhancingthe display response characteristics in the display device comprisingthe data driver to achieve remarkable display image quality.

In the embodiment mentioned above concerning the display pixels EP,despite the fact the configuration corresponding to the current sinkingmethod flows the light generation drive current generated by the pixeldriver circuits DCz in the direction drawn from the organic EL devicesOEL side, this invention is not limited to this applies to theconfiguration shown in FIGS. 4-5 mentioned above and shown in FIG. 45.Thus, the configuration corresponding to a current application methodwhich supplies the light generation current generated by the pixeldriver circuits DCz so it flows (pours) in the direction of the organicEL devices OEL from the current generation section 20 z is alsoapplicable. Moreover, in the configuration (Reference FIG. 41) of thedisplay device as illustrated in the embodiment mentioned above, theother end side (+V connection side) of the current generator isconnected to the low potential voltage (voltage to ground), and it isset up so the reference current Iref may be drawn in this low potentialvoltage direction from the display panel (display pixels EP) side.

Subsequently, another example of the configuration in the display deviceconcerning this embodiment will be explained.

In the above, where the configuration of the first or the secondembodiment of the current generation circuit mentioned above wereapplied to the pixel driver circuits DCz or DCz′ and explained. However,this invention is not restricted to this and can be applied to theconfiguration in the third or fourth embodiment of the currentgeneration circuit stated above to the pixel driver circuits DCz or DCz′as other examples of the configuration. When the display dataconstitutes a specified value, the circuit can be equipped with theorganic EL devices OEL (optical elements) which are configured to supplya specified voltage Vbk (black display voltage) or a specified voltageVr (reset voltage) the same as the fourth through eighth embodiments ofthe data driver mentioned above. These example display device and pixeldriver circuit configurations are shown in FIGS. 46-47.

FIG. 46 is an outline block diagram showing another example of theconfiguration in the display device of this embodiment.

FIG. 47 is a circuit arrangement drawing showing another embodiment ofthe pixel driver circuit applied to the display device in thisembodiment.

Specifically, the display panel 110E′ as shown in FIG. 46 as opposed tothe configuration of the display panel 110E in FIG. 41 mentioned above,the specified voltage (black display voltage Vbk or reset voltage Vr) issupplied externally and wired for applying the specified voltage to eachof the display pixels EPa. Each of the display pixels EPa comprise aconfiguration equal to the third or fourth embodiments of the currentgeneration circuit mentioned above and shown in FIG. 47, which have acircuit arrangement provided with pixel driver circuits DCza comprisingan input terminal Vin for the specified voltage Vbk or Vr. In the caseof these circumstances in the fourth through eighth embodiments of thedata driver stated above, when the display data consists of a specifiedvalue, it is a specified voltage to the organic EL devices OEL (opticalelements) supplied as the black display voltage Vbk or the reset voltageVr.

In each embodiment mentioned above which applied a 4-bit digital signalfor the display data, while the case example performed the displayoperation of 2⁴=16 gradations, needless to say this invention is notrestricted to this and can be applied to an image display of many moregradations.

Furthermore, though in the case explained where the current generationcircuit related to this invention was applied to the data driver or thepixel driver circuits of the display device in the embodiment mentionedabove, the present invention is not limited to such an example ofapplication. For example, such as a printer head arranged and formedwith a lot of light emitting elements. By supplying current which has apredetermined current value, this invention also can be appliedadvantageously to a driver circuit of a device comprisingmultifunctional elements which operates in a state of predetermineddrive according to that current value.

<<The Configuration of the Field-Effect Transistors>>

Next, the configuration of the Thin-Film Field-Effect Transistorsapplicable to the current generation circuit related to this invention,and the pixel driver circuit formed in the display panel of the displaydevice will be explained.

FIGS. 48A-48B are drawings showing the basic circuit and voltage-currentcharacteristics of an Nch Thin-Film Field-Effect Transistor in aconventional configuration.

FIGS. 49A-49B are drawings showing the basic circuit and voltage-currentcharacteristics of a Pch Thin-Film Field-Effect Transistor in aconventional configuration.

Each of the write-in current generation circuits which forms the datadriver in each of the embodiments mentioned above (current generationcircuits) or set to a pixel driver circuit (current generation section)which forms the display panel, for example, as shown in FIG. 3, FIG. 5,FIG. 16 and FIG. 21 set as a configuration for the pixel driver circuitscomprised of Nch (n-channel type) or Pch (p-channel type) Thin-FilmField-Effect Transistors (also commonly known as a FET; and whenincluding the terminology Thin-Film Transistor known as a TFT); and acurrent mirror circuit comprised reference current transistors andgradation current transistors.

Here, the dashed lines in FIGS. 48B and 49B, show ideally the Thin-FilmNch transistors which form the current mirror circuit or the pixeldriver circuit for light generation drive, as well as show the voltagecurrent-characteristics of the Thin-Film Pch transistors required forthe saturation inclination for the voltage Vds between the source-drainconsisting of constant drain current in a specified voltage region(saturation voltage region). However, as shown in FIGS. 48A and 49A tosubstantiate using a basic circuit and, actually, as shown in FIGS. 48Band 49B as a continuous line, once the drain current shows a saturationinclination with buildup of the voltage Vds between the source-drain,the inclination increases gradually as shown. This, for example, is inview of the fact that there have been beneficial improvements in thespeed, low-power consumption, high integration and the like in recentyears. The Field-Effect Transistor and the like which has asilicon-on-insulator (SOI) semiconductor layer configuration hasprogressed rapidly through research and development. By means ofinducing collision ionization near the isolation region where theelectric field concentrates and as a result of flowing in (pouring in)and accumulation (floating substrate effect) of the carrier (AnNch>n-channel type transistor with an electron deficiency or hole and aPch>p-channel type transistor electron) accordingly generated in thechannel region (Equivalent to body region), the threshold voltage fallsand drain current increases which is thought to be based on the “Kink”phenomenon (a parasitic phenomenon called “Kink” consisting of athreshold voltage shift).

Therefore, the favorable saturation characteristics of the drain current(voltage-current characteristic) are no longer acquired according to theincreased phenomenon of the drain current by such kink phenomenon, andset in a current mirror circuit. In a current generation circuit whichrequires the ratio of the current value of the gradation current toreference current for the desired design value. That is, the embodimentsmentioned above are not set up as the ratio of the channel width of thetransistor, and the current values of the write-in current andluminescent drive current at the time of a light generation operationdiffer in the transistor for the luminescent drive. Therefore, lightgeneration operation in each of the display pixels may be performed bythe suitable luminosity gradation based on the display data, anddegradation of the display image quality may be caused.

Hereinafter, the transistor for the light drive in the pixel circuitsDCy will be explained. Accordingly, explanation will also refer to thepixel driver circuit DCy shown in FIG. 21.

FIGS. 50A-50B are drawings showing the connection between thevoltage-current characteristics in the transistor for the lightgeneration drive (Pch transistor) and the current value of the draincurrent (light generation drive current) which can be set at the time ofthe write-in operation and the light generation operation. Specifically,because the Pch transistor Tr81 performs “OFF” operation and the Nchtransistors Tr82 and Tr84 perform an “ON” operation in the pixel drivercircuits DCy shown in FIG. 21 by applying a high-level scanning signalVsel to the scanning lines SL at the time of the write-in operation asmentioned above, the write-in current Ipix flows into the organic ELdevices OEL via the Nch transistor Tr82 and the Pch transistor Tr83. Atthis time, because the Nch transistor Tr84 is in an “ON” state, thevoltage between gate-source Vgs of the Pch transistor Tr83 (betweencontacts Nya-Nyb) and the voltage between source-drain Vds (betweencontacts Nya-Nya) become the same. The operating point on thevoltage-current characteristic curve at this time constitutes ACw withinthe region. For example, FIG. 50A shows the saturation characteristics.

Conversely, at the time of light generation operation, because the Pchtransistor Tr81 performs and “ON” operation and the Nch transistors Tr82and Tr84 perform and “OFF” operation, by applying the scanning signalVsel of a low-level to the scanning lines SL, the light generation drivecurrent flows into the organic EL devices OEL via the Pch transistorsTr81 and Tr83 from the high potential voltage connected to the voltagecontact +V. Since the Nch transistor Tr84 is in an “OFF” state at thispoint, the gate voltage (potential of contact Nyb) of the Pch transistorTr83 will be in a floating condition. As for the voltage between thegate-source of the Pch transistor Tr83, the potential at the time of thewrite-in operation ahead of the scanning signal Vsel switches over andis held as the electric charge accumulated in capacitor Cy at the timeof the above-mentioned write-in operation. Therefore, as shown in FIGS.50A and 50B, at this time the operating point on the voltage-currentcharacteristics curve becomes ACh which has moved into the low voltagedirection (FIG. 50B right side) within the saturation region rather thanthe operating point ACw. Here, the transition to the operating point AChfrom the operating point ACw from being changed within the saturationregion is not concerned with the value of the voltage −(Vds) between thesource-drain, but of the almost constant drain current −(Ids) flow.Ideally set up at the time of the above-mentioned write-in operation,the current (light generation drive current) which flows into theorganic EL devices OEL will be controlled by a current value almostequivalent to the current (write-in current Ipix) held.

However, when it has the characteristics in which the drain current−(Ids) increases gradually as the voltage-current characteristic of Pchtransistor Tr83 shown in FIG. 49B and the absolute value of the voltage−(Vds) between the source-drain increases, the current (light generationdrive current) which flows into the organic EL devices OEL will become adifferent value from the current set up at the time of the write-inoperation (write-in current Ipix). It will become impossible for thisreason, to perform light generation operation of each of the displaypixels by the suitable luminosity gradation based on display data.

Then, in this embodiment, in order to control the kink phenomenon whichwas mentioned above, the present invention configuration appliesThin-Film Transistors (TFTs) which have at least the so-called bodyterminal configuration, whereby the body region and source region of SOItype Field-Effect Transistors are electrically connected to referencecurrent transistors in current generation circuits, and gradationcurrent transistors together with transistors for light generation drivein pixel driver circuits.

<<Body Terminal Configuration>>

Here, a Pch (p-channel type) transistor which has a body terminalconfiguration will be described in detail.

FIGS. 51A-51B are schematic diagrams showing a level surfaceconfiguration of a Pch Thin-Film transistor which has a body terminalconfiguration.

FIGS. 52A-52D are schematic diagrams showing a cross-sectionalconfiguration of a Pch Thin-Film transistor which has a body terminalconfiguration.

Here, FIG. 51A exhibits the planar structure of the active layer formedon a semiconductor substrate and FIG. 51B expresses a planar structurein the state where the electrode is formed on an active layer. Also,FIG. 52A shows the configuration of the A-A cross-sectional surface ofthe configuration shown in FIG. 51B. FIG. 52B shows the configuration ofthe B-B cross-sectional surface of the configuration in FIG. 51B. FIGS.52C and 52D are circuit notations which show a Pch transistor and an Nchtransistor which have a body terminal configuration.

Needless to say, the Field-Effect Transistor that has the body terminalstructure shown here may have other transistor structures that have thedevice characteristics illustrated in the example applications of thecurrent generation circuits or the display device disclosed in thisinvention, but have equivalent component characteristics.

A Pch (p-channel type) Thin-Film Transistor which has the body terminalconfiguration as shown in FIG. 51A-51B and FIG. 52A-52B has aconfiguration comprised of the junction formation terminal region RT(n+) which protrudes from the channel region Rohn in a verticaldirection (the up-and-down direction of FIG. 51A) to the opposite axis(horizontal direction of FIG. 51A) of the source region RS and the drainregion RD, while the source region RS (p+) and the drain region RD (p+)are formed and separated in an Nch semiconductor layer (active layerRac) constituted in the entire surface side of silicon and the like onan Nch semiconductor substrate sub via the insulator layer insS acrossthe channel region Rchn (body region).

Additionally, on the upper part the active layer Rac, as shown in FIG.51B and FIG. 52A-52B, comprises a single body terminal electrode EBprovided with ohmic contacts formed in the source region RS and theterminal region RT; the gate electrode EG is formed via the gateinsulator layer insG on the upper part of the channel region Rchn; andthe drain electrode ED ohmic contact to the drain region RD. An Nchtransistor which has such a body terminal configuration is notated withthe circuit symbol as shown in FIG. 52C.

Although a Pch type Thin-Film Transistor which has a body terminalconfiguration mentioned above was explained, an Nch type Thin-FilmTransistor which has a body terminal configuration equipped as shown inFIGS. 51A-51B and FIGS. 52A-52B is an almost equivalent configuration.While the source region (n+) and the drain region (n+) are formed in theactive layer which consists of a Pch semiconductor layer across thechannel region, the terminal region (p+) has a configuration with thejunction formation protruding from the channel region. The configurationof the gate electrode, the drain electrode, and the body terminalelectrode is the same as that of in the case of the above-mentioned Pchtransistor. An Nch transistor which has such a body terminalconfiguration is notated with the circuit symbol as shown in FIG. 52D.

FIGS. 53A-53B are drawings showing the basic circuit of an Nch Thin-FilmTransistor which has a body terminal configuration and thevoltage-current characteristics.

FIGS. 54A-54B are drawings showing the basic circuit of a Pch Thin-FilmTransistor which has a body terminal configuration and thevoltage-current characteristics.

When verified using a basic circuit as shown in FIG. 53A and FIG. 54Aconsisting of Nch (n-channel type) transistors which have such a bodyterminal configuration, and the voltage-current characteristics in Pch(p-channel type) Thin-Film Transistors, as shown in FIG. 53B and FIG.54B, in the specified voltage region, the voltage Vds, −(Vds) betweenthe source-drain, the drain current Ids, −(Ids) showed a favorablesaturation inclination.

This is because generation of the kink phenomenon is controlled as theminority carrier (An Nch>n-channel type transistor with an electrondeficiency or hole and a Pch>p-channel type transistor electron) flowsinto the source region RS via the body terminal electrode EB in theelectron and electron hole pairs produced near the boundary of thechannel region Rchn and the drain region RD as mentioned above, thus theaccumulation to the channel region Rchn is controlled and the decreasein the threshold voltage of a Field-Effect Transistor is alleviated.

Therefore, according to the present invention, the solution is to applyField-Effect Transistors which have such a voltage-currentcharacteristic to the transistors for light generation drive in thecurrent mirror circuits of the current generation sections in each ofthe embodiments mentioned above, as well as the pixel driver circuits.Particularly, when configured in the current generation circuits, thedata driver of the display devices, the display panels and the likerelated to this invention, because the write-in current and lightgeneration drive current have a suitable current value corresponding tothe current held based on the display data or gradation data aregenerable. Thus, the light generation operation in each of the displaypixels can be performed by a suitable luminosity gradation based on thedisplay data and enhancement in the display image quality can beachieved.

While the present invention has been described with reference to thepreferred embodiments, it is intended that the invention be not limitedby any of the details of the description thereof.

As this invention may be embodied in several forms without departingfrom the spirit of the essential characteristics thereof, the presentembodiments are therefore illustrative and not restrictive, since thescope of the invention is defined by the appended claims rather than bythe description preceding them, and all changes that fall within meetsand bounds of the claims, or equivalence of such meets and boundsthereof are intended to be embraced by the claims.

What is claimed is:
 1. A display device for displaying image informationcorresponding to display signals derived from digital signals, thedisplay device comprising: a display panel comprising a plurality ofsignal lines and a plurality of scanning lines which intersectperpendicularly with each other and a plurality of display pixels withoptical elements arranged near intersecting points of the plurality ofsignal lines and the plurality of scanning lines; a scanning drivercircuit for sequentially applying a line at a time a scanning signal toeach of the plurality of scanning lines for setting the plurality ofdisplay pixels in a selective state a line at a time; and a signaldriver circuit comprising a plurality of current generation circuits,wherein each of the current generation circuits comprises: a gradationcurrent generation circuit which generates a plurality of gradationcurrents corresponding to each bit of the display signals based on apredetermined constant reference current; a drive current generationcircuit which generates a drive current that is selected based on theplurality of gradation currents corresponding to each bit of the displaysignals, and that is supplied to a corresponding signal line; and aspecified state setting circuit which supplies a specified voltage tothe corresponding signal line to drive the corresponding optical elementin a specified operating state instead of supplying the drive current,when the display signals have a specified value that sets all of theplurality of gradation currents in a non-selection state.
 2. The displaydevice according to claim 1, wherein each current generation circuitsets a signal polarity of the drive current so that the drive currentflows in a direction drawn from a display pixels side.
 3. The displaydevice according to claim 1, wherein each current generation circuitsets a signal polarity of the drive current so the drive current flowsin a direction poured into the display pixels.
 4. The display deviceaccording to claim 1, wherein each of a plurality of current generationcircuits in the signal driver circuit is provided corresponding to eachof a plurality of the display pixels of each scanning line of thedisplay panel.
 5. The display device according to claim 4, wherein thecurrent generation circuits supply the corresponding drive currentssimultaneously to each of the plurality of pixels of each scanning line.6. The display device according to claim 1, wherein each currentgeneration circuit further comprises a signal holding circuit whichtakes in and holds a display signal.
 7. The display device according toclaim 6, wherein the drive current generation circuit generates thedrive current based on a value of the display signal held in the signalholding circuit.
 8. The display device according to claim 6, wherein thesignal holding circuit comprises a plurality of latch circuits whichtake in and hold each bit of the display signals, and outputs an outputsignal responsive to each bit.
 9. The display device according to claim1, wherein the drive current generation circuit comprises a switchingcircuit for selecting a current from the plurality of gradation currentsin response to each bit value of the display signals.
 10. The displaydevice according to claim 9, wherein the current generation circuitfurther comprises a signal holding circuit for taking in and holding adisplay signal.
 11. The display device according to claim 10, whereinthe signal holding circuit comprises a plurality of latch circuits whichtake in and hold each bit of the display signals and output an outputsignal responsive to each bit; and wherein the switching circuit selectsfrom the gradation currents and generates the drive current based on theoutput of the plurality of latch circuits.
 12. The display deviceaccording to claim 1, wherein a current value of the plurality ofgradation currents have a different ratio with respect to each otherspecified by 2^(n) where n=0, 1, 2 and 3, . . . .
 13. The display deviceaccording to claim 1, wherein each gradation current generation circuitcomprises a plurality of gradation current transistors for generatingthe plurality of gradation currents.
 14. The display device according toclaim 13, wherein each of the plurality of gradation current transistorsdiffers in a transistor size and each control terminal thereof isconnected in parallel; and wherein the gradation currents flow in acurrent path of each of the gradation current transistors.
 15. Thedisplay device according to claim 14, wherein a channel width of eachgradation current transistor is set at a different ratio with respect toeach other specified by 2^(n) where n=0, 1, 2 and 3, . . . .
 16. Thedisplay device according to claim 13, wherein each gradation currentgeneration circuit comprises a reference voltage generation circuit forgenerating a reference voltage based on the constant reference current.17. The display device according to claim 16, wherein the referencevoltage generation circuit comprises a reference current transistor forgenerating the reference voltage for control terminals; wherein thereference current is supplied to a current path; and wherein a referencecurrent transistor control terminal is connected in common to thecontrol terminals of the plurality of gradation current transistors. 18.The display device according to claim 17, wherein the reference currenttransistor and the plurality of gradation current transistors constitutea current mirror circuit.
 19. The display device according to claim 17,wherein at least any one of the reference current transistor and theplurality of gradation current transistors has a transistor structurewhich comprises: a channel region in a semiconductor layer formed by aninsulator layer in an entire surface side of a semiconductor substrate,a source region and a drain region formed across the channel region, aterminal region formed and projected from the channel region in avertical direction toward an opposite axis of the source region and thedrain region; a gate electrode formed by a gate insulator layer on saidchannel region; a drain electrode electrically connected to the drainregion; and a single body terminal electrode electrically connected tothe source region and the terminal region.
 20. The display deviceaccording to claim 1, wherein each gradation current generation circuitfurther comprises a reference voltage generation circuit for generatinga reference voltage based on the constant reference current.
 21. Thedisplay device according to claim 20, wherein the reference voltagegeneration circuit comprises an electric charge storage circuit forstoring an electric charge in response to a current component of thereference current.
 22. The display device according to claim 1, whereinthe signal driver circuit comprises: a reference current supply line forsupplying the reference current; and a structure in which the referencecurrent is supplied to the plurality of gradation current generationcircuits via the reference current supply line.
 23. The display deviceaccording to claim 22, wherein each gradation generation circuitcomprises a supply control switching circuit for controlling a supplystate of the reference current from the reference current supply line tothe gradation current generation circuit; and wherein the supply controlswitching circuits selectively perform switching control so thereference current may be supplied only to any one gradation currentgeneration circuit of the plurality of gradation current generationcircuits.
 24. The display device according to claim 23, wherein eachcurrent generation circuit comprises a signal holding circuit for takingin and holding a display signal.
 25. The display device according toclaim 24, wherein a supply control switching circuit timing of theswitching control synchronizes with a timing of the signal holdingcircuit of taking in and holding the display signal.
 26. The displaydevice according to claim 1, wherein the specified voltage is a voltagewhich drives the corresponding optical element in a minimum gradationstate.
 27. The display device according to claim 1, wherein thespecified state setting circuit comprises: a specified digital valuejudgment section for judging whether or not the display signals have thespecified value, and a specified voltage application section forapplying the specified voltage to the corresponding signal line based ona result of the judgment by the specified digital value judgmentsection.
 28. The display device according to claim 27, wherein thespecified digital value judgment section performs the judgment ofwhether or not said display signals have the specified value based on alogical sum of each bit value of the digital signals of the displaysignals.
 29. The display device according to claim 1, wherein eachcurrent generation circuit further comprises a reset circuit forapplying a predetermined reset voltage to the corresponding signal linein advance of a timing when the drive current is supplied to the signalline.
 30. The display device according to claim 29, wherein the resetvoltage is at least a low potential voltage for discharging an electriccharge stored up in a capacitative element attached to the correspondingoptical element in the corresponding display pixel, and for initializingthe optical element.
 31. The display device according to claim 29,wherein the drive current is generated by selecting the gradationcurrents according to each bit of the display signals; and wherein thereset voltage is applied when a display signal specified valuepresupposes non-selection of all of the plurality of gradation currents.32. The display device according to claim 31, wherein the reset circuitcomprises: a specified digital value judgment section for judgingwhether or not the display signals have the specified value; and a resetvoltage application section for applying the reset voltage to thecorresponding signal line based on a result of the judgment by thespecified digital value judgment section.
 33. The display deviceaccording to claim 32, wherein the specified digital value judgmentsection performs the judgment of whether or not the display signals havethe specified value based on a logical sum of each bit value of thedigital signals of the display signals.
 34. The display device accordingto claim 1, wherein the optical elements in the display pixels compriselight emitting elements for accomplishing a light generation operationby way of luminosity gradation according to a current value of thesupplied drive currents.
 35. The display device according to claim 34,wherein the light emitting elements comprise organic electroluminescentelements.
 36. The display device according to claim 34, wherein thedisplay pixels comprise at least a pixel driver circuit; and wherein thepixel driver circuit includes: a voltage holding circuit for holding avoltage component in response to the drive current supplied from thesignal driver circuit; and a current supply circuit for supplyingluminescent drive current to the corresponding light emitting elementbased on the voltage component held in the voltage holding circuit andfor making the light emitting element emit light.
 37. The display deviceaccording to claim 36, wherein the pixel driver circuit comprises anelectric discharge circuit for discharging an electric charge responsiveto the voltage component stored up in the voltage holding circuit. 38.The display device according to claim 36, wherein the current supplycircuit comprises a transistor for use of luminescent drive forsupplying luminescent current to the corresponding light emittingelement, the transistor for use of luminescent drive has a transistorstructure which comprises: a channel region in a semiconductor layerformed by an insulator layer in an entire surface side of asemiconductor substrate; a source region and a drain region formedacross the channel region; a terminal region formed and projected fromthe channel region in a vertical direction toward an opposite axis ofthe source region and the drain region; a gate electrode formed by agate insulator layer on the channel region; a drain electrodeelectrically connected to the drain region; and a single body terminalelectrode electrically connected to the source region and the terminalregion.
 39. A method for driving a display device which displays imageinformation corresponding to display signals derived from digitalsignals on a display panel comprising a plurality of display pixelsprovided with optical elements arranged near intersecting points of aplurality of signal lines and a plurality of scanning lines, the methodcomprising: taking in and holding the display signals corresponding tothe plurality of display pixels; generating a plurality of gradationcurrents corresponding to each bit of the display signals based on apredetermined constant reference current; generating a drive currentselected based on the plurality of gradation currents corresponding toeach bit of the display signals held; supplying the generated drivecurrent to the corresponding signal line; judging whether or not thedisplay signals have a specified value that sets all of the plurality ofgradation currents in a non-selection state; and when it is judged thatthe display signals have the specified value, supplying a specifiedvoltage to the corresponding signal line to drive the correspondingdisplay pixel in a specified operating state instead of supplying thegenerated drive current.
 40. The method for driving the display deviceaccording to claim 39, wherein a current value of the plurality ofgradation currents have a different ratio with respect to each otherspecified by 2^(n) where n=0, 1, 2, and 3, . . . .
 41. The method fordriving the display device according to claim 39, wherein the drivecurrent is generated by selecting and integrating the correspondinggradation currents in response to each bit value of the display signals.42. The method for driving the display device according to claim 39,wherein a signal polarity of the drive current is set so the drivecurrent flows in a direction drawn from a display pixel side.
 43. Themethod for driving the display device according to claim 39, wherein asignal polarity of the drive current is set so the drive current flowsin a direction poured into the display pixels.
 44. The method fordriving the display device according to claim 39, wherein the opticalelements in the display pixels comprise light emitting elements whichaccomplish light generation operation by way of luminosity gradationaccording to a current value of the supplied drive currents.
 45. Themethod for driving the display device according to claim 44, wherein thelight emitting elements comprise organic electroluminescent elements.46. The method for driving the display device according to claim 44,further comprising: holding a voltage component corresponding to thedrive current; and supplying a luminescent drive current to thecorresponding light emitting element based on the held voltage componentthereby making the light emitting element emit light.
 47. The method fordriving the display device according to claim 39, wherein the specifiedvoltage is a voltage setting which drives the corresponding opticalelement in a minimum gradation state.
 48. The method for driving thedisplay device according to claim 39, further comprising applying apredetermined reset voltage to the signal lines at the timing beforeapplying the drive current to each signal line.
 49. The method fordriving the display device according to claim 48, wherein the resetvoltage is at least a low potential voltage for initializing each loadand discharging a charge stored up in a capacitative element attached toeach load.
 50. The method for driving the display device according toclaim 49, wherein the drive current is generated by selecting thegradation currents according to each bit of the display signals, andwherein the reset voltage is applied when the display signals have thespecified value which presupposes non-selection of all of the gradationcurrents.
 51. The method for driving the display device according toclaim 50, further comprising: judging whether the display signals havethe specified value or not, and applying the reset voltage to thecorresponding signal line when it is judged that the display signalshave the specified value.
 52. The method for driving the display deviceaccording to claim 39, further comprising discharging a charge stored upin a capacitative element attached to the optical elements in thedisplay pixels at a timing before applying the drive current to eachsignal line.